From b3a1bde4db9889feb116330bff21214811c940e4 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 14 Feb 2007 19:14:56 +0100 Subject: [ARM] 4108/2: Allow multiple GIC interrupt controllers in a system The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/platsmp.c | 2 +- arch/arm/mach-realview/realview_eb.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-realview') diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index b8484e15dac..709a9b1ac63 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -52,7 +52,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE)); + gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); /* * let the primary processor know we're out of the diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 9741b4d3c9c..b6a6f68cb69 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -143,8 +143,8 @@ static void __init gic_init_irq(void) writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8); writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); #endif - gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE)); - gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE)); + gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); + gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); } static void __init realview_eb_init(void) -- cgit v1.2.3 From 3edf22ab34e1fdffc8c0c7c7b7da4d0aebdba118 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 14 Feb 2007 19:18:09 +0100 Subject: [ARM] 4190/2: Add the secondary GIC support for the RealView/EB MPCore platform This patch adds the registration of the secondary GIC on the baseboard, together with the IRQ chaining setup. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/realview_eb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/mach-realview') diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index b6a6f68cb69..00139143dcc 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -57,7 +57,21 @@ static struct map_desc realview_eb_io_desc[] __initdata = { .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), .length = SZ_4K, .type = MT_DEVICE, + }, +#ifdef CONFIG_REALVIEW_MPCORE + { + .virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, }, { + .virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif + { .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), .length = SZ_4K, @@ -145,6 +159,11 @@ static void __init gic_init_irq(void) #endif gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); +#ifdef CONFIG_REALVIEW_MPCORE + gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64); + gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE)); + gic_cascade_irq(1, IRQ_EB_IRQ1); +#endif } static void __init realview_eb_init(void) -- cgit v1.2.3 From 4b17244c133689ad0cbdca37ce3e15068f120428 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 14 Feb 2007 19:20:28 +0100 Subject: [ARM] 4109/2: Add support for the RealView/EB MPCore revC platform The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/Kconfig | 10 ++++++++++ arch/arm/mach-realview/realview_eb.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-realview') diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 17f5f4439fe..68bc6b226ec 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -16,4 +16,14 @@ config REALVIEW_MPCORE kernel built with this option enabled is not compatible with other tiles. +config REALVIEW_MPCORE_REVB + bool "Support MPcore RevB tile" + depends on REALVIEW_MPCORE + default n + help + Enable support for the MPCore RevB tile on the Realview platform. + Since there are device address differences, a + kernel built with this option enabled is not compatible with + other tiles. + endmenu diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 00139143dcc..effe243454e 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -152,9 +152,9 @@ static void __init gic_init_irq(void) #ifdef CONFIG_REALVIEW_MPCORE unsigned int pldctrl; writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); - pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8); + pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); pldctrl |= 0x00800000; /* New irq mode */ - writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8); + writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); #endif gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); -- cgit v1.2.3