From 06cc9dbf238fb43cf66d1bd068cfe6e81f669317 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:06:34 +0100 Subject: [ARM] S3C24XX: Split pll code out of regs-clock.h Move the PLL calculation code into it's own header file for re-use with the other plat-s3c24xx based systems such as the S3C24A0. Note, we change the name of s3c2410_get_pll to the more generically named s3c24xx_get_pll as well as the related defintions. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2412/s3c2412.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-s3c2412') diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 0e144484f4b..f26e3d215d0 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -47,6 +47,7 @@ #include #include #include +#include #ifndef CONFIG_CPU_S3C2412_ONLY void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; @@ -165,7 +166,7 @@ void __init s3c2412_init_clocks(int xtal) /* now we've got our machine bits initialised, work out what * clocks we've got */ - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); + fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); clk_mpll.rate = fclk; -- cgit v1.2.3