From 5a7732b94a6ddea17c60c53529813a658a2ee7e1 Mon Sep 17 00:00:00 2001 From: Balaji Rao Date: Sun, 22 Feb 2009 04:40:03 +0000 Subject: gta02_use_new_fiq_and_hdq_stuff.patch Signed-off-by: Balaji Rao --- arch/arm/mach-s3c2442/Kconfig | 10 +- arch/arm/mach-s3c2442/fiq_c_isr.c | 321 ---------------------------- arch/arm/mach-s3c2442/fiq_c_isr.h | 76 ------- arch/arm/mach-s3c2442/mach-gta02.c | 426 +++++++++++++++---------------------- 4 files changed, 168 insertions(+), 665 deletions(-) delete mode 100644 arch/arm/mach-s3c2442/fiq_c_isr.c delete mode 100644 arch/arm/mach-s3c2442/fiq_c_isr.h (limited to 'arch/arm/mach-s3c2442') diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index 991ed6a2d0b..0d2dd03491c 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -17,15 +17,6 @@ config CPU_S3C2442 help Support for S3C2442 Samsung Mobile CPU based systems. -config S3C2440_C_FIQ - bool "FIQ ISR support in C" - depends on ARCH_S3C2410 - select FIQ - help - Support for S3C2440 FIQ support in C -- see - ./arch/arm/mach-s3c2440/fiq_c_isr.c - - menu "S3C2442 Machines" @@ -43,6 +34,7 @@ config MACH_NEO1973_GTA02 select MACH_NEO1973 select S3C_PWM select S3C2410_CLOCK + select FIQ help Say Y here if you are using the FIC Neo1973 GSM Phone diff --git a/arch/arm/mach-s3c2442/fiq_c_isr.c b/arch/arm/mach-s3c2442/fiq_c_isr.c deleted file mode 100644 index e1728300ad0..00000000000 --- a/arch/arm/mach-s3c2442/fiq_c_isr.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright 2007 Andy Green - * S3C modfifications - * Copyright 2008 Andy Green - */ - -#include -#include -#include -#include -#include "fiq_c_isr.h" -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include - -/* - * Major Caveats for using FIQ - * --------------------------- - * - * 1) it CANNOT touch any vmalloc()'d memory, only memory - * that was kmalloc()'d. Static allocations in the monolithic kernel - * are kmalloc()'d so they are okay. You can touch memory-mapped IO, but - * the pointer for it has to have been stored in kmalloc'd memory. The - * reason for this is simple: every now and then Linux turns off interrupts - * and reorders the paging tables. If a FIQ happens during this time, the - * virtual memory space can be partly or entirely disordered or missing. - * - * 2) Because vmalloc() is used when a module is inserted, THIS FIQ - * ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module. But the way - * it is set up, you can all to enable and disable it from your module - * and intercommunicate with it through struct fiq_ipc - * fiq_ipc which you can define in - * asm/archfiq_ipc_type.h. The reason is the same as above, a - * FIQ could happen while even the ISR is not present in virtual memory - * space due to pagetables being changed at the time. - * - * 3) You can't call any Linux API code except simple macros - * - understand that FIQ can come in at any time, no matter what - * state of undress the kernel may privately be in, thinking it - * locked the door by turning off interrupts... FIQ is an - * unstoppable monster force (which is its value) - * - they are not vmalloc()'d memory safe - * - they might do crazy stuff like sleep: FIQ pisses fire and - * is not interested in 'sleep' that the weak seem to need - * - calling APIs from FIQ can re-enter un-renterable things - * - summary: you cannot interoperate with linux APIs directly in the FIQ ISR - * - * If you follow these rules, it is fantastic, an extremely powerful, solid, - * genuine hard realtime feature. - * - */ - -/* more than enough to cover our jump instruction to the isr */ -#define SIZEOF_FIQ_JUMP 4 - -#define FIQ_VECTOR 0xffff001c - -/* we put the stack at the area after the FIQ vector */ -#define FIQ_STACK_SIZE 256 - -/* only one FIQ ISR possible, okay to do these here */ -u32 _fiq_ack_mask; /* used by isr exit define */ -unsigned long _fiq_count_fiqs; /* used by isr exit define */ -static int _fiq_irq; /* private ; irq index we were started with, or 0 */ -struct s3c2410_pwm pwm_timer_fiq; -int _fiq_timer_index; -u16 _fiq_timer_divisor; -u8 fiq_ready; - -/* this function must live in the monolithic kernel somewhere! A module is - * NOT good enough! - */ -extern void __attribute__ ((naked)) s3c2440_fiq_isr(void); - -static void fiq_set_vector_and_regs(void); - - -/* this is copied into the hard FIQ vector during init */ - -static void __attribute__ ((naked)) s3c2440_FIQ_Branch(void) -{ - asm __volatile__ ( - "mov pc, r8 ; " - ); -} - -/* sysfs */ - -static ssize_t show_count(struct device *dev, struct device_attribute *attr, - char *buf) -{ - return sprintf(buf, "%ld\n", _fiq_count_fiqs); -} - -static DEVICE_ATTR(count, 0444, show_count, NULL); - -static struct attribute *s3c2440_fiq_sysfs_entries[] = { - &dev_attr_count.attr, - NULL -}; - -static struct attribute_group s3c2440_fiq_attr_group = { - .name = "fiq", - .attrs = s3c2440_fiq_sysfs_entries, -}; - -/* - * call this from your kernel module to set up the FIQ ISR to service FIQs, - * You need to have configured your FIQ input pin before anything will happen - * - * call it with, eg, IRQ_TIMER3 from asm-arm/arch-s3c2410/irqs.h - * - * you still need to clear the source interrupt in S3C2410_INTMSK to get - * anything good happening - */ -static int fiq_init_irq_source(int irq_index_fiq) -{ - int rc = 0; - - if (!irq_index_fiq) /* no interrupt */ - goto bail; - - local_fiq_disable(); - - _fiq_irq = irq_index_fiq; - _fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET); - _fiq_timer_index = (irq_index_fiq - IRQ_TIMER0); - - /* set up the timer to operate as a pwm device */ - - rc = s3c2410_pwm_init(&pwm_timer_fiq); - if (rc) - goto bail; - - pwm_timer_fiq.timerid = PWM0 + _fiq_timer_index; - pwm_timer_fiq.prescaler = (6 - 1) / 2; - pwm_timer_fiq.divider = S3C2410_TCFG1_MUX3_DIV2; - /* default rate == ~32us */ - pwm_timer_fiq.counter = pwm_timer_fiq.comparer = 3000; - - rc = s3c2410_pwm_enable(&pwm_timer_fiq); - if (rc) - goto bail; - - s3c2410_pwm_start(&pwm_timer_fiq); - - _fiq_timer_divisor = 0xffff; /* so kick will work initially */ - - /* let our selected interrupt be a magic FIQ interrupt */ - __raw_writel(_fiq_ack_mask, S3C2410_INTMOD); - - /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */ - local_fiq_enable(); -bail: - return rc; -} - - -/* call this from your kernel module to disable generation of FIQ actions */ -static void fiq_disable_irq_source(void) -{ - /* nothing makes FIQ any more */ - __raw_writel(0, S3C2410_INTMOD); - local_fiq_disable(); - _fiq_irq = 0; /* no active source interrupt now either */ -} - -/* - * fiq_kick() forces a FIQ event to happen shortly after leaving the routine - */ -void fiq_kick(void) -{ - unsigned long flags; - u32 tcon; - - if (!fiq_ready) { - printk(KERN_ERR "fiq_kick called before fiq probed\n"); - return; - } - - /* we have to take care about FIQ because this modification is - * non-atomic, FIQ could come in after the read and before the - * writeback and its changes to the register would be lost - * (platform INTMSK mod code is taken care of already) - */ - local_save_flags(flags); - local_fiq_disable(); - /* allow FIQs to resume */ - __raw_writel(__raw_readl(S3C2410_INTMSK) & - ~(1 << (_fiq_irq - S3C2410_CPUIRQ_OFFSET)), - S3C2410_INTMSK); - tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START; - /* fake the timer to a count of 1 */ - __raw_writel(1, S3C2410_TCNTB(_fiq_timer_index)); - __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON); - __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START, - S3C2410_TCON); - __raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON); - local_irq_restore(flags); -} -EXPORT_SYMBOL_GPL(fiq_kick); - - - - -static int __init sc32440_fiq_probe(struct platform_device *pdev) -{ - struct resource *r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - struct sc32440_fiq_platform_data *pdata = pdev->dev.platform_data; - int ret; - - if (!r) - return -EIO; - - /* configure for the interrupt we are meant to use */ - printk(KERN_INFO "Enabling FIQ using irq %d\n", r->start); - - fiq_set_vector_and_regs(); - fiq_init_irq_source(r->start); - - ret = sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group); - if (ret) - return ret; - - fiq_ready = 1; - - /* - * if wanted, users can defer registration of devices - * that depend on FIQ until after we register, and can use our - * device as parent so suspend-resume ordering is correct - */ - if (pdata->attach_child_devices) - (pdata->attach_child_devices)(&pdev->dev); - - return 0; -} - -static int sc32440_fiq_remove(struct platform_device *pdev) -{ - fiq_disable_irq_source(); - sysfs_remove_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group); - - return 0; -} - -static void fiq_set_vector_and_regs(void) -{ - struct pt_regs regs; - - /* prep the special FIQ mode regs */ - memset(®s, 0, sizeof(regs)); - regs.ARM_r8 = (unsigned long)s3c2440_fiq_isr; - regs.ARM_r10 = FIQ_VECTOR + SIZEOF_FIQ_JUMP; - regs.ARM_sp = FIQ_VECTOR + SIZEOF_FIQ_JUMP + FIQ_STACK_SIZE - 4; - - /* copy our jump to the real ISR into the hard vector address */ - set_fiq_handler(s3c2440_FIQ_Branch, SIZEOF_FIQ_JUMP); - - /* set up the special FIQ-mode-only registers from our regs */ - set_fiq_regs(®s); -} - -#ifdef CONFIG_PM -static int sc32440_fiq_suspend(struct platform_device *pdev, pm_message_t state) -{ - /* nothing makes FIQ any more */ - __raw_writel(0, S3C2410_INTMOD); - local_fiq_disable(); - - return 0; -} - -static int sc32440_fiq_resume(struct platform_device *pdev) -{ - fiq_set_vector_and_regs(); - fiq_init_irq_source(_fiq_irq); - return 0; -} -#else -#define sc32440_fiq_suspend NULL -#define sc32440_fiq_resume NULL -#endif - -static struct platform_driver sc32440_fiq_driver = { - .driver = { - .name = "sc32440_fiq", - .owner = THIS_MODULE, - }, - - .probe = sc32440_fiq_probe, - .remove = __devexit_p(sc32440_fiq_remove), - .suspend = sc32440_fiq_suspend, - .resume = sc32440_fiq_resume, -}; - -static int __init sc32440_fiq_init(void) -{ - fiq_set_vector_and_regs(); - - return platform_driver_register(&sc32440_fiq_driver); -} - -static void __exit sc32440_fiq_exit(void) -{ - fiq_disable_irq_source(); -} - -MODULE_AUTHOR("Andy Green "); -MODULE_LICENSE("GPL"); - -module_init(sc32440_fiq_init); -module_exit(sc32440_fiq_exit); diff --git a/arch/arm/mach-s3c2442/fiq_c_isr.h b/arch/arm/mach-s3c2442/fiq_c_isr.h deleted file mode 100644 index e92b103cdfb..00000000000 --- a/arch/arm/mach-s3c2442/fiq_c_isr.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _LINUX_FIQ_C_ISR_H -#define _LINUX_FIQ_C_ISR_H - -#include -#include - -extern unsigned long _fiq_count_fiqs; -extern u32 _fiq_ack_mask; -extern int _fiq_timer_index; -extern u16 _fiq_timer_divisor; - -/* platform data */ - -struct sc32440_fiq_platform_data { - /* - * give an opportunity to use us as parent for - * devices that depend on us - */ - void (*attach_child_devices)(struct device *parent_device); -}; - -/* This CANNOT be implemented in a module -- it has to be used in code - * included in the monolithic kernel - */ - -#define FIQ_HANDLER_START() \ -void __attribute__ ((naked)) s3c2440_fiq_isr(void) \ -{\ - /*\ - * you can declare local vars here, take care to set the frame size\ - * below accordingly if there are more than a few dozen bytes of them\ - */\ - -/* stick your locals here :-) - * Do NOT initialize them here! define them and initialize them after - * FIQ_HANDLER_ENTRY() is done. - */ - -#define FIQ_HANDLER_ENTRY(LOCALS, FRAME) \ - const int _FIQ_FRAME_SIZE = FRAME; \ - /* entry takes care to store registers we will be treading on here */\ - asm __volatile__ (\ - /* stash FIQ and r0-r8 normal regs */\ - "stmdb sp!, {r0-r12, lr};"\ - /* allow SP to get some space */\ - "sub sp, sp, %1 ;"\ - /* !! THIS SETS THE FRAME, adjust to > sizeof locals */\ - "sub fp, sp, %0 ;"\ - :\ - : "rI" (LOCALS), "rI" (FRAME)\ - :"r9"\ - ); - -/* stick your ISR code here and then end with... */ - -#define FIQ_HANDLER_END() \ - _fiq_count_fiqs++;\ - __raw_writel(_fiq_ack_mask, S3C2410_SRCPND);\ -\ - /* exit back to normal mode restoring everything */\ - asm __volatile__ (\ - /* pop our allocation */\ - "add sp, sp, %0 ;"\ - /* return FIQ regs back to pristine state\ - * and get normal regs back\ - */\ - "ldmia sp!, {r0-r12, lr};"\ -\ - /* return */\ - "subs pc, lr, #4;"\ - : \ - : "rI" (_FIQ_FRAME_SIZE) \ - );\ -} - -#endif /* _LINUX_FIQ_C_ISR_H */ diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index ffc72fb37a9..ff102fa863d 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -76,6 +76,7 @@ #include #include #include +#include #include @@ -89,14 +90,13 @@ #include #include #include +#include #include #include -#include -#include "fiq_c_isr.h" -#include +#include #include #include @@ -110,243 +110,148 @@ #include <../drivers/input/touchscreen/ts_filter_group.h> #endif +#include + +#include + /* arbitrates which sensor IRQ owns the shared SPI bus */ static spinlock_t motion_irq_lock; -/* define FIQ IPC struct */ -/* - * contains stuff FIQ ISR modifies and normal kernel code can see and use - * this is defined in , you should customize - * the definition in there and include the same definition in your kernel - * module that wants to interoperate with your FIQ code. + +/* ------------------------------------------------------------------------------- + * GTA02 FIQ related + * + * Calls into vibrator and hdq and based on the return values + * determines if we the FIQ source be kept alive */ -struct fiq_ipc fiq_ipc; -EXPORT_SYMBOL(fiq_ipc); #define DIVISOR_FROM_US(x) ((x) << 3) -#define FIQ_DIVISOR_VIBRATOR DIVISOR_FROM_US(100) +#ifdef CONFIG_HDQ_GPIO_BITBANG +#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(20) +extern int hdq_fiq_handler(void); +#endif -#ifdef CONFIG_GTA02_HDQ -/* HDQ specific */ -#define HDQ_SAMPLE_PERIOD_US 20 -/* private HDQ FSM state -- all other info interesting for caller in fiq_ipc */ -static enum hdq_bitbang_states hdq_state; -static u8 hdq_ctr; -static u8 hdq_ctr2; -static u8 hdq_bit; -static u8 hdq_shifter; -static u8 hdq_tx_data_done; - -#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(HDQ_SAMPLE_PERIOD_US) +#ifdef CONFIG_LEDS_NEO1973_VIBRATOR +#define FIQ_DIVISOR_VIBRATOR DIVISOR_FROM_US(100) +extern int neo1973_vibrator_fiq_handler(void); #endif -/* define FIQ ISR */ -FIQ_HANDLER_START() -/* define your locals here -- no initializers though */ - u16 divisor; -FIQ_HANDLER_ENTRY(64, 64) -/* Your ISR here :-) */ - divisor = 0xffff; +/* Global data related to our fiq source */ +static u32 gta02_fiq_ack_mask; +static struct s3c2410_pwm gta02_fiq_pwm_timer; +static u16 gta02_fiq_timer_index; +static int gta02_fiq_irq; + +static void gta02_fiq_handler(void) +{ + u16 divisor = 0xffff; /* Vibrator servicing */ - if (fiq_ipc.vib_pwm_latched || fiq_ipc.vib_pwm) { /* not idle */ - if (((u8)_fiq_count_fiqs) == fiq_ipc.vib_pwm_latched) - neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 0); - if (((u8)_fiq_count_fiqs) == 0) { - fiq_ipc.vib_pwm_latched = fiq_ipc.vib_pwm; - if (fiq_ipc.vib_pwm_latched) - neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 1); - } + /* disable further timer interrupts if nobody has any work + * or adjust rate according to who still has work + * + * CAUTION: it means forground code must disable FIQ around + * its own non-atomic S3C2410_INTMSK changes... not common + * thankfully and taken care of by the fiq-basis patch + */ + +#ifdef CONFIG_LEDS_NEO1973_VIBRATOR + if (neo1973_vibrator_fiq_handler()) divisor = FIQ_DIVISOR_VIBRATOR; - } +#endif -#ifdef CONFIG_GTA02_HDQ - /* HDQ servicing */ +#ifdef CONFIG_HDQ_GPIO_BITBANG + if (hdq_fiq_handler()) + divisor = FIQ_DIVISOR_HDQ; +#endif - switch (hdq_state) { - case HDQB_IDLE: - if (fiq_ipc.hdq_request_ctr == fiq_ipc.hdq_transaction_ctr) - break; - hdq_ctr = 210 / HDQ_SAMPLE_PERIOD_US; - s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0); - s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT); - hdq_tx_data_done = 0; - hdq_state = HDQB_TX_BREAK; - break; + if (divisor == 0xffff) /* mask the fiq irq source */ + __raw_writel(__raw_readl(S3C2410_INTMSK) | gta02_fiq_ack_mask, + S3C2410_INTMSK); + else /* still working, maybe at a different rate */ + __raw_writel(divisor, S3C2410_TCNTB(gta02_fiq_timer_index)); - case HDQB_TX_BREAK: /* issue low for > 190us */ - if (--hdq_ctr == 0) { - hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; - hdq_state = HDQB_TX_BREAK_RECOVERY; - s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1); - } - break; + __raw_writel(gta02_fiq_ack_mask, S3C2410_SRCPND); +} - case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */ - if (--hdq_ctr) - break; - hdq_shifter = fiq_ipc.hdq_ads; - hdq_bit = 8; /* 8 bits of ads / rw */ - hdq_tx_data_done = 0; /* doing ads */ - /* fallthru on last one */ - case HDQB_ADS_CALC: - if (hdq_shifter & 1) - hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US; - else - hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US; - /* carefully precompute the other phase length */ - hdq_ctr2 = (210 - (hdq_ctr * HDQ_SAMPLE_PERIOD_US)) / - HDQ_SAMPLE_PERIOD_US; - hdq_state = HDQB_ADS_LOW; - hdq_shifter >>= 1; - hdq_bit--; - s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0); - break; +static void gta02_fiq_kick(void) +{ + unsigned long flags; + u32 tcon; + + /* we have to take care about FIQ because this modification is + * non-atomic, FIQ could come in after the read and before the + * writeback and its changes to the register would be lost + * (platform INTMSK mod code is taken care of already) + */ + local_save_flags(flags); + local_fiq_disable(); + /* allow FIQs to resume */ + __raw_writel(__raw_readl(S3C2410_INTMSK) & + ~(1 << (gta02_fiq_irq - S3C2410_CPUIRQ_OFFSET)), + S3C2410_INTMSK); + tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START; + /* fake the timer to a count of 1 */ + __raw_writel(1, S3C2410_TCNTB(gta02_fiq_timer_index)); + __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON); + __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START, + S3C2410_TCON); + __raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON); + local_irq_restore(flags); +} - case HDQB_ADS_LOW: - if (--hdq_ctr) - break; - s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1); - hdq_state = HDQB_ADS_HIGH; - break; +static int gta02_fiq_enable(void) +{ + int irq_index_fiq = IRQ_TIMER3; + int rc = 0; - case HDQB_ADS_HIGH: - if (--hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */ - break; - if (hdq_bit) { /* more bits to do */ - hdq_state = HDQB_ADS_CALC; - break; - } - /* no more bits, wait it out until hdq_ctr2 exhausted */ - if (hdq_ctr2) - break; - /* ok no more bits and very last state */ - hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US; - /* FIXME 0 = read */ - if (fiq_ipc.hdq_ads & 0x80) { /* write the byte out */ - /* set delay before payload */ - hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US; - /* already high, no need to write */ - hdq_state = HDQB_WAIT_TX; - break; - } - /* read the next byte */ - hdq_bit = 8; /* 8 bits of data */ - hdq_ctr = 3000 / HDQ_SAMPLE_PERIOD_US; - hdq_state = HDQB_WAIT_RX; - s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT); - break; + local_fiq_disable(); - case HDQB_WAIT_TX: /* issue low for > 40us */ - if (--hdq_ctr) - break; - if (!hdq_tx_data_done) { /* was that the data sent? */ - hdq_tx_data_done++; - hdq_shifter = fiq_ipc.hdq_tx_data; - hdq_bit = 8; /* 8 bits of data */ - hdq_state = HDQB_ADS_CALC; /* start sending */ - break; - } - fiq_ipc.hdq_error = 0; - fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr; - hdq_state = HDQB_IDLE; /* all tx is done */ - /* idle in input mode, it's pulled up by 10K */ - s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT); - break; + gta02_fiq_irq = irq_index_fiq; + gta02_fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET); + gta02_fiq_timer_index = (irq_index_fiq - IRQ_TIMER0); - case HDQB_WAIT_RX: /* wait for battery to talk to us */ - if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin) == 0) { - /* it talks to us! */ - hdq_ctr2 = 1; - hdq_bit = 8; /* 8 bits of data */ - /* timeout */ - hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US; - hdq_state = HDQB_DATA_RX_LOW; - break; - } - if (--hdq_ctr == 0) { /* timed out, error */ - fiq_ipc.hdq_error = 1; - fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr; - hdq_state = HDQB_IDLE; /* abort */ - } - break; + /* set up the timer to operate as a pwm device */ - /* - * HDQ basically works by measuring the low time of the bit cell - * 32-50us --> '1', 80 - 145us --> '0' - */ + rc = s3c2410_pwm_init(>a02_fiq_pwm_timer); + if (rc) + goto bail; - case HDQB_DATA_RX_LOW: - if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) { - fiq_ipc.hdq_rx_data >>= 1; - if (hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US)) - fiq_ipc.hdq_rx_data |= 0x80; - - if (--hdq_bit == 0) { - fiq_ipc.hdq_error = 0; - fiq_ipc.hdq_transaction_ctr = - fiq_ipc.hdq_request_ctr; - - hdq_state = HDQB_IDLE; - } else - hdq_state = HDQB_DATA_RX_HIGH; - /* timeout */ - hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US; - hdq_ctr2 = 1; - break; - } - hdq_ctr2++; - if (--hdq_ctr) - break; - /* timed out, error */ - fiq_ipc.hdq_error = 2; - fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr; - hdq_state = HDQB_IDLE; /* abort */ - break; + gta02_fiq_pwm_timer.timerid = PWM0 + gta02_fiq_timer_index; + gta02_fiq_pwm_timer.prescaler = (6 - 1) / 2; + gta02_fiq_pwm_timer.divider = S3C2410_TCFG1_MUX3_DIV2; + /* default rate == ~32us */ + gta02_fiq_pwm_timer.counter = gta02_fiq_pwm_timer.comparer = 3000; - case HDQB_DATA_RX_HIGH: - if (!s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) { - /* it talks to us! */ - hdq_ctr2 = 1; - /* timeout */ - hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US; - hdq_state = HDQB_DATA_RX_LOW; - break; - } - if (--hdq_ctr) - break; - /* timed out, error */ - fiq_ipc.hdq_error = 3; - fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr; + rc = s3c2410_pwm_enable(>a02_fiq_pwm_timer); + if (rc) + goto bail; - /* we're in input mode already */ - hdq_state = HDQB_IDLE; /* abort */ - break; - } + s3c2410_pwm_start(>a02_fiq_pwm_timer); - if (hdq_state != HDQB_IDLE) /* ie, not idle */ - if (divisor > FIQ_DIVISOR_HDQ) - divisor = FIQ_DIVISOR_HDQ; /* keep us going */ -#endif + /* let our selected interrupt be a magic FIQ interrupt */ + __raw_writel(gta02_fiq_ack_mask, S3C2410_INTMOD); - /* disable further timer interrupts if nobody has any work - * or adjust rate according to who still has work - * - * CAUTION: it means forground code must disable FIQ around - * its own non-atomic S3C2410_INTMSK changes... not common - * thankfully and taken care of by the fiq-basis patch - */ - if (divisor == 0xffff) /* mask the fiq irq source */ - __raw_writel(__raw_readl(S3C2410_INTMSK) | _fiq_ack_mask, - S3C2410_INTMSK); - else /* still working, maybe at a different rate */ - __raw_writel(divisor, S3C2410_TCNTB(_fiq_timer_index)); - _fiq_timer_divisor = divisor; + /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */ + local_fiq_enable(); -FIQ_HANDLER_END() + set_fiq_c_handler(gta02_fiq_handler); + +bail: + printk(KERN_ERR "Count not initialize FIQ for GTA02\n"); + return rc; +} +static void gta02_fiq_disable(void) +{ + __raw_writel(0, S3C2410_INTMOD); + local_fiq_disable(); + gta02_fiq_irq = 0; /* no active source interrupt now either */ + +} +/* -------------------- /GTA02 FIQ Handler ------------------------------------- */ /* * this gets called every 1ms when we paniced. @@ -497,9 +402,9 @@ static int gta02_get_charger_active_status(void) struct bq27000_platform_data bq27000_pdata = { .name = "battery", .rsense_mohms = 20, - .hdq_read = gta02hdq_read, - .hdq_write = gta02hdq_write, - .hdq_initialized = gta02hdq_initialized, + .hdq_read = hdq_read, + .hdq_write = hdq_write, + .hdq_initialized = hdq_initialized, .get_charger_online_status = gta02_get_charger_online_status, .get_charger_active_status = gta02_get_charger_active_status }; @@ -807,7 +712,7 @@ static void mangle_pmu_pdata_by_system_rev(void) } } -#ifdef CONFIG_GTA02_HDQ +#ifdef CONFIG_HDQ_GPIO_BITBANG /* HDQ */ static void gta02_hdq_attach_child_devices(struct device *parent_device) @@ -823,6 +728,27 @@ static void gta02_hdq_attach_child_devices(struct device *parent_device) } } +static void gta02_hdq_gpio_direction_out(void) +{ + s3c2410_gpio_cfgpin(GTA02v5_GPIO_HDQ, S3C2410_GPIO_OUTPUT); +} + +static void gta02_hdq_gpio_direction_in(void) +{ + s3c2410_gpio_cfgpin(GTA02v5_GPIO_HDQ, S3C2410_GPIO_INPUT); +} + +static void gta02_hdq_gpio_set_value(int val) +{ + + s3c2410_gpio_setpin(GTA02v5_GPIO_HDQ, val); +} + +static int gta02_hdq_gpio_get_value(void) +{ + return s3c2410_gpio_getpin(GTA02v5_GPIO_HDQ); +} + static struct resource gta02_hdq_resources[] = { [0] = { .start = GTA02v5_GPIO_HDQ, @@ -830,12 +756,21 @@ static struct resource gta02_hdq_resources[] = { }, }; -struct gta02_hdq_platform_data gta02_hdq_platform_data = { - .attach_child_devices = gta02_hdq_attach_child_devices +struct hdq_platform_data gta02_hdq_platform_data = { + .attach_child_devices = gta02_hdq_attach_child_devices, + .gpio_dir_out = gta02_hdq_gpio_direction_out, + .gpio_dir_in = gta02_hdq_gpio_direction_in, + .gpio_set = gta02_hdq_gpio_set_value, + .gpio_get = gta02_hdq_gpio_get_value, + + .enable_fiq = gta02_fiq_enable, + .disable_fiq = gta02_fiq_disable, + .kick_fiq = gta02_fiq_kick, + }; struct platform_device gta02_hdq_device = { - .name = "gta02-hdq", + .name = "hdq", .num_resources = 1, .resource = gta02_hdq_resources, .dev = { @@ -852,52 +787,19 @@ static struct resource gta02_vibrator_resources[] = { .end = GTA02_GPIO_VIBRATOR_ON, }, }; +struct neo1973_vib_platform_data gta02_vib_pdata = { + .enable_fiq = gta02_fiq_enable, + .disable_fiq = gta02_fiq_disable, + .kick_fiq = gta02_fiq_kick, +}; static struct platform_device gta02_vibrator_dev = { .name = "neo1973-vibrator", .num_resources = ARRAY_SIZE(gta02_vibrator_resources), .resource = gta02_vibrator_resources, -}; - -/* FIQ, used PWM regs, so not child of PWM */ - -static void gta02_fiq_attach_child_devices(struct device *parent_device) -{ -#ifdef CONFIG_GTA02_HDQ - switch (system_rev) { - case GTA02v5_SYSTEM_REV: - case GTA02v6_SYSTEM_REV: - gta02_hdq_device.dev.parent = parent_device; - platform_device_register(>a02_hdq_device); - gta02_vibrator_dev.dev.parent = parent_device; - platform_device_register(>a02_vibrator_dev); - break; - default: - break; - } -#endif -} - - -static struct resource sc32440_fiq_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, - .start = IRQ_TIMER3, - .end = IRQ_TIMER3, - }, -}; - -struct sc32440_fiq_platform_data gta02_sc32440_fiq_platform_data = { - .attach_child_devices = gta02_fiq_attach_child_devices -}; - -struct platform_device sc32440_fiq_device = { - .name = "sc32440_fiq", - .num_resources = 1, - .resource = sc32440_fiq_resources, - .dev = { - .platform_data = >a02_sc32440_fiq_platform_data, - }, + .dev = { + .platform_data = >a02_vib_pdata, + }, }; /* NOR Flash */ @@ -1648,7 +1550,6 @@ static struct platform_device *gta02_devices[] __initdata = { &s3c_device_nand, >a02_nor_flash, - &sc32440_fiq_device, &s3c24xx_pwm_device, >a02_led_dev, >a02_pm_wlan_dev, /* not dependent on PMU */ @@ -1789,6 +1690,13 @@ static void __init gta02_machine_init(void) enable_irq_wake(GTA02_IRQ_WLAN_GPIO1); pm_power_off = gta02_poweroff; + + /* Register the HDQ and vibrator as children of pwm device */ + gta02_vibrator_dev.dev.parent = &s3c24xx_pwm_device.dev; + gta02_hdq_device.dev.parent = &s3c24xx_pwm_device.dev; + platform_device_register(>a02_hdq_device); + platform_device_register(>a02_vibrator_dev); + } void DEBUG_LED(int n) -- cgit v1.2.3