From 7092fc38ee770251aed361572bf6bed05fcf3ee2 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 20 Jul 2007 11:42:29 +0100 Subject: [ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm/mm/Kconfig') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index d377376d6ee..7cc32b70711 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. -config CPU_L2CACHE_DISABLE - bool "Disable level 2 cache" - depends on CPU_V7 - help - Say Y here to disable the level 2 cache. If unsure, say N. - config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 -- cgit v1.2.3