From 8799ee9f49f6171fd58f4d64f8c067ca49006a5d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 29 Jun 2006 18:24:21 +0100 Subject: [ARM] Set bit 4 on section mappings correctly depending on CPU On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King --- arch/arm/mm/proc-arm925.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/mm/proc-arm925.S') diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index aaa9f985b24..a28da8f0578 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -522,6 +522,10 @@ cpu_arm925_name: __arm925_proc_info: .long 0x54029250 .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ @@ -541,6 +545,10 @@ __arm925_proc_info: __arm915_proc_info: .long 0x54029150 .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ -- cgit v1.2.3