From 0516e4643cd22fc9f535aef02ad1de66c382c93b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 30 Apr 2009 17:06:20 +0100 Subject: [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It configures the L2 cache auxiliary control register so that the Write Allocate mode for the L2 cache is disabled. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 370baa7a0f0..f2305441e7d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -193,6 +193,11 @@ __v7_setup: orr r10, r10, #(1 << 5) @ set L1NEON to 1 orr r10, r10, #(1 << 9) @ set PLDNOP to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_460075 + mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register #endif mov r10, #0 #ifdef HARVARD_CACHE -- cgit v1.2.3