From 52c543f90c4095dff71dc125017594b61a753069 Mon Sep 17 00:00:00 2001 From: Quinn Jensen Date: Mon, 9 Jul 2007 22:06:53 +0100 Subject: [ARM] 4461/1: MXC platform and i.MX31ADS core support This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/plat-mxc/Kconfig | 20 +++++++++++ arch/arm/plat-mxc/Makefile | 10 ++++++ arch/arm/plat-mxc/irq.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 arch/arm/plat-mxc/Kconfig create mode 100644 arch/arm/plat-mxc/Makefile create mode 100644 arch/arm/plat-mxc/irq.c (limited to 'arch/arm/plat-mxc') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig new file mode 100644 index 00000000000..03a65c0dfb6 --- /dev/null +++ b/arch/arm/plat-mxc/Kconfig @@ -0,0 +1,20 @@ +if ARCH_MXC + +menu "Freescale MXC Implementations" + +choice + prompt "MXC/iMX System Type" + default 0 + +config ARCH_MX3 + bool "MX3-based" + help + This enables support for systems based on the Freescale i.MX3 family + +endchoice + +source "arch/arm/mach-mx3/Kconfig" + +endmenu + +endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile new file mode 100644 index 00000000000..66ad9c2b6d6 --- /dev/null +++ b/arch/arm/plat-mxc/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# + +# Common support +obj-y := irq.o + +obj-m := +obj-n := +obj- := diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c new file mode 100644 index 00000000000..87d253bc3d3 --- /dev/null +++ b/arch/arm/plat-mxc/irq.c @@ -0,0 +1,83 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * Disable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ +static void mxc_mask_irq(unsigned int irq) +{ + __raw_writel(irq, AVIC_INTDISNUM); +} + +/*! + * Enable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ +static void mxc_unmask_irq(unsigned int irq) +{ + __raw_writel(irq, AVIC_INTENNUM); +} + +static struct irq_chip mxc_avic_chip = { + .mask_ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, +}; + +/*! + * This function initializes the AVIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init mxc_init_irq(void) +{ + int i; + u32 reg; + + /* put the AVIC into the reset value with + * all interrupts disabled + */ + __raw_writel(0, AVIC_INTCNTL); + __raw_writel(0x1f, AVIC_NIMASK); + + /* disable all interrupts */ + __raw_writel(0, AVIC_INTENABLEH); + __raw_writel(0, AVIC_INTENABLEL); + + /* all IRQ no FIQ */ + __raw_writel(0, AVIC_INTTYPEH); + __raw_writel(0, AVIC_INTTYPEL); + for (i = 0; i < MXC_MAX_INT_LINES; i++) { + set_irq_chip(i, &mxc_avic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ + reg = __raw_readl(AVIC_NIPRIORITY6); + reg |= (0xF << 28); + __raw_writel(reg, AVIC_NIPRIORITY6); + + printk(KERN_INFO "MXC IRQ initialized\n"); +} -- cgit v1.2.3