From b3bb4f688c225d9455bbd59e98f634f98c1074d0 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 23 Apr 2009 11:10:49 -0700 Subject: ARM: OMAP2/3: GPIO: do not attempt to wake-enable The GPIO IRQ enable/disable path attempts to also enable IRQ wake support for the parent GPIO bank IRQ as well. However, since there is no 'set_wake' hook for the bank IRQs, these calls will always fail. Also, since the enable will fail on the suspend path, the disable on the resume path will trigger unbalanced enable/disable warnings. This was discovered in the suspend/resume path on OMAP3/Beagle using the gpio-keys driver which disables/re-enables GPIO IRQ wakeups in the suspend/resume path. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-omap/gpio.c') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d3fa41e3d8c..210a1c04555 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -921,13 +921,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) case METHOD_MPUIO: case METHOD_GPIO_1610: spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif @@ -940,13 +937,10 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) return -EINVAL; } spin_lock_irqsave(&bank->lock, flags); - if (enable) { + if (enable) bank->suspend_wakeup |= (1 << gpio); - enable_irq_wake(bank->irq); - } else { - disable_irq_wake(bank->irq); + else bank->suspend_wakeup &= ~(1 << gpio); - } spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif -- cgit v1.2.3 From bedfd15410a331e4183d3d926bb944682cad61f3 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 23 Apr 2009 11:10:50 -0700 Subject: ARM: OMAP3: Fixed spurious IRQ issue for GPIO interrupts Flush posted write to IRQSTATUS register in GPIO IRQ handler. This eliminates the below error for all peripherals that use GPIO interrupts. <4>Spurious irq 95: 0xffffffdf, please flush posted write for irq 31 Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/gpio.c') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 210a1c04555..17d7afe42b8 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -758,8 +758,12 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) /* Workaround for clearing DSP GPIO interrupts to allow retention */ #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) + reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; if (cpu_is_omap24xx() || cpu_is_omap34xx()) - __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); + __raw_writel(gpio_mask, reg); + + /* Flush posted write for the irq status to avoid spurious interrupts */ + __raw_readl(reg); #endif } -- cgit v1.2.3