From 778edbe124a99ef9825ae2341eb855f8de49e258 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:06:38 +0100 Subject: [ARM] S3C24XX: cpufreq suspend/resume support. Support suspend and resume properly with the cpufreq driver enabled. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/clock.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-s3c24xx/clock.c') diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 334e696200b..a4a0a67a307 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c @@ -47,6 +47,8 @@ #include #include +#include + #include #include #include @@ -327,24 +329,24 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) /* initalise all the clocks */ -int __init s3c24xx_setup_clocks(unsigned long xtal, - unsigned long fclk, - unsigned long hclk, - unsigned long pclk) +void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, + unsigned long hclk, + unsigned long pclk) { - printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); - - /* initialise the main system clocks */ - - clk_xtal.rate = xtal; - clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); + clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), + clk_xtal.rate); clk_mpll.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; clk_f.rate = fclk; +} - /* assume uart clocks are correctly setup */ +int __init s3c24xx_register_baseclocks(unsigned long xtal) +{ + printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); + + clk_xtal.rate = xtal; /* register our clocks */ @@ -368,3 +370,4 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, return 0; } + -- cgit v1.2.3