From bdd0f5f06e7647b545bec3ead2fa2a5fcdf0f0f9 Mon Sep 17 00:00:00 2001 From: Davide Rizzo Date: Sat, 3 May 2008 07:53:14 +0100 Subject: [ARM] 4882/2: Correction for S3C2410 clkout generation This is a correction for 2 small bugs for the Samsung S3C2410 ARM9 SoC clocks generator Signed-off-by: Davide Rizzo Acked-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/plat-s3c24xx/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-s3c24xx/clock.c') diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index d84167fb33b..3ac8d8d781b 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c @@ -411,7 +411,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) clk->parent = parent; - if (clk == &s3c24xx_dclk0) + if (clk == &s3c24xx_clkout0) mask = S3C2410_MISCCR_CLK0_MASK; else { source <<= 4; @@ -437,7 +437,7 @@ struct clk s3c24xx_dclk0 = { struct clk s3c24xx_dclk1 = { .name = "dclk1", .id = -1, - .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .ctrlbit = S3C2410_DCLKCON_DCLK1EN, .enable = s3c24xx_dclk_enable, .set_parent = s3c24xx_dclk_setparent, .set_rate = s3c24xx_set_dclk_rate, -- cgit v1.2.3