From f833228c21602f9466cbfbf13465f05b67b07a7f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 3 Nov 2008 14:56:25 +0000 Subject: [ARM] S3C64XX: Fix MMC0 clock source register mask Fix the definition of the MMC0 register shift and mask in the CLKSRC register. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-s3c64xx/include') diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 78938a5e1d2..b1082c16324 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -205,8 +205,8 @@ #define S3C6400_CLKSRC_MMC2_SHIFT (22) #define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) #define S3C6400_CLKSRC_MMC1_SHIFT (20) -#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1) -#define S3C6400_CLKSRC_MMC0_SHIFT (1) +#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) +#define S3C6400_CLKSRC_MMC0_SHIFT (18) #define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) #define S3C6400_CLKSRC_SPI1_SHIFT (16) #define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) -- cgit v1.2.3