From 05225d2426dd3cf614a642741fe7f0c5ad7702fa Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Wed, 25 Feb 2009 00:41:14 +0000 Subject: S3C64XX: Fix HCLK_GATE bit definitions Fix the definitions of HCLK_GATE bits, which had SDMA0/1 named SDMA1/2 and the definitions of bits 26..29 in the wrong order. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-s3c64xx') diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d41e33..0aefe3b9993 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -89,10 +89,10 @@ /* HCLK GATE Registers */ #define S3C_CLKCON_HCLK_BUS (1<<30) -#define S3C_CLKCON_HCLK_SECUR (1<<29) -#define S3C_CLKCON_HCLK_SDMA1 (1<<28) -#define S3C_CLKCON_HCLK_SDMA2 (1<<27) -#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) #define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR0 (1<<23) -- cgit v1.2.3