From c80ce2d52b1d11ccb29eddb3fc1345cd49ccfc5a Mon Sep 17 00:00:00 2001 From: Jaswinder Singh Date: Fri, 25 Jul 2008 13:48:38 +0530 Subject: avr32: Introducing asm/syscalls.h Declaring arch-dependent syscalls for avr32 architecture Signed-off-by: Jaswinder Singh Signed-off-by: Haavard Skinnemoen --- arch/avr32/kernel/process.c | 1 + arch/avr32/kernel/signal.c | 1 + arch/avr32/kernel/sys_avr32.c | 1 + arch/avr32/mm/cache.c | 1 + 4 files changed, 4 insertions(+) (limited to 'arch/avr32') diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c index 134d5302b6d..43ae555ecb3 100644 --- a/arch/avr32/kernel/process.c +++ b/arch/avr32/kernel/process.c @@ -18,6 +18,7 @@ #include #include +#include #include diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c index c5b11f9067f..803d7be0938 100644 --- a/arch/avr32/kernel/signal.c +++ b/arch/avr32/kernel/signal.c @@ -19,6 +19,7 @@ #include #include +#include #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) diff --git a/arch/avr32/kernel/sys_avr32.c b/arch/avr32/kernel/sys_avr32.c index 8e8911e55c8..5d2daeaf356 100644 --- a/arch/avr32/kernel/sys_avr32.c +++ b/arch/avr32/kernel/sys_avr32.c @@ -13,6 +13,7 @@ #include #include +#include asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, diff --git a/arch/avr32/mm/cache.c b/arch/avr32/mm/cache.c index 15a4e5e142c..24a74d1ca7d 100644 --- a/arch/avr32/mm/cache.c +++ b/arch/avr32/mm/cache.c @@ -13,6 +13,7 @@ #include #include #include +#include /* * If you attempt to flush anything more than this, you need superuser -- cgit v1.2.3 From 5f6333bd6ed3c855c725ab389eeed8bf7c198798 Mon Sep 17 00:00:00 2001 From: Kay Sievers Date: Fri, 7 Nov 2008 01:37:21 +0100 Subject: avr: struct device - replace bus_id with dev_name(), dev_set_name() (I did not compile or test it, please let me know, or help fixing it, if something is wrong with the conversion) This patch is part of a larger patch series which will remove the "char bus_id[20]" name string from struct device. The device name is managed in the kobject anyway, and without any size limitation, and just needlessly copied into "struct device". To set and read the device name dev_name(dev) and dev_set_name(dev) must be used. If your code uses static kobjects, which it shouldn't do, "const char *init_name" can be used to statically provide the name the registered device should have. At registration time, the init_name field is cleared, to enforce the use of dev_name(dev) to access the device name at a later time. We need to get rid of all occurrences of bus_id in the entire tree to be able to enable the new interface. Please apply this patch, and possibly convert any remaining remaining occurrences of bus_id. We want to submit a patch to -next, which will remove bus_id from "struct device", to find the remaining pieces to convert, and finally switch over to the new api, which will remove the 20 bytes array and does no longer have a size limitation. Thanks, Kay From: Kay Sievers Subject: avr: struct device - replace bus_id with dev_name(), dev_set_name() Cc: Haavard Skinnemoen Acked-by: Greg Kroah-Hartman Signed-off-by: Kay Sievers Signed-off-by: Haavard Skinnemoen --- arch/avr32/mach-at32ap/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/avr32') diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c index 138a00a2a2d..442f08c5e64 100644 --- a/arch/avr32/mach-at32ap/clock.c +++ b/arch/avr32/mach-at32ap/clock.c @@ -198,7 +198,7 @@ dump_clock(struct clk *parent, struct clkinf *r) unsigned i; /* skip clocks coupled to devices that aren't registered */ - if (parent->dev && !parent->dev->bus_id[0] && !parent->users) + if (parent->dev && !dev_name(parent->dev) && !parent->users) return; /* name */ @@ -214,7 +214,7 @@ dump_clock(struct clk *parent, struct clkinf *r) parent->users ? "on" : "off", /* NOTE: not-paranoid!! */ clk_get_rate(parent)); if (parent->dev) - seq_printf(r->s, ", for %s", parent->dev->bus_id); + seq_printf(r->s, ", for %s", dev_name(parent->dev)); seq_printf(r->s, "\n"); /* cost of this scan is small, but not linear... */ -- cgit v1.2.3 From 8d3d3fb922624e1dfd0b96f669b7a1a0c6c10b95 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Wed, 3 Dec 2008 12:38:32 +0000 Subject: MIMC200: Remove deprecated call This patch removes a call to the deprecated function at32_add_system_devices(). Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen --- arch/avr32/boards/mimc200/setup.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/avr32') diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c index 397cbb8f44c..c060d4d2839 100644 --- a/arch/avr32/boards/mimc200/setup.c +++ b/arch/avr32/boards/mimc200/setup.c @@ -207,8 +207,6 @@ static int __init mimc200_init(void) * reserve any pins for it. */ - at32_add_system_devices(); - at32_add_device_usart(0); at32_add_device_usart(1); at32_add_device_usart(2); -- cgit v1.2.3 From 45f926912fb960c7c09c12906143b9dbaddf58cb Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 6 Nov 2008 11:19:21 +0100 Subject: favr-32: Remove deprecated call at32_add_system_devices() is deprecated, so remove the call to it. Signed-off-by: Haavard Skinnemoen --- arch/avr32/boards/favr-32/setup.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/avr32') diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c index 7538f3d2b9e..ff8235a30ec 100644 --- a/arch/avr32/boards/favr-32/setup.c +++ b/arch/avr32/boards/favr-32/setup.c @@ -327,8 +327,6 @@ static int __init favr32_init(void) at32_select_gpio(GPIO_PIN_PB(3), 0); /* IRQ from ADS7843 */ - at32_add_system_devices(); - at32_add_device_usart(0); set_hw_addr(at32_add_device_eth(0, ð_data[0])); -- cgit v1.2.3 From adde42b5834ed367ef7455d465bd9610190ad2a0 Mon Sep 17 00:00:00 2001 From: Alex Raimondi Date: Tue, 4 Nov 2008 23:37:10 +0100 Subject: avr32: Allow reserving multiple pins at once at32_reserve_pin now takes an u32 bitmask rather than a single pin. This allows to reserve multiple pins at once. Remove (undocumented) SDCS (pin PE26) from reservation in board setup code. Signed-off-by: Alex Raimondi Signed-off-by: Haavard Skinnemoen --- arch/avr32/boards/atstk1000/atstk1002.c | 18 +----------------- arch/avr32/boards/atstk1000/atstk1003.c | 18 +----------------- arch/avr32/boards/favr-32/setup.c | 18 +----------------- arch/avr32/mach-at32ap/include/mach/at32ap700x.h | 3 +++ arch/avr32/mach-at32ap/include/mach/portmux.h | 2 +- arch/avr32/mach-at32ap/pio.c | 19 +++++++++++++------ 6 files changed, 20 insertions(+), 58 deletions(-) (limited to 'arch/avr32') diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c index 5c5cdf3b464..11e7800c163 100644 --- a/arch/avr32/boards/atstk1000/atstk1002.c +++ b/arch/avr32/boards/atstk1000/atstk1002.c @@ -287,23 +287,7 @@ static int __init atstk1002_init(void) * ATSTK1000 uses 32-bit SDRAM interface. Reserve the * SDRAM-specific pins so that nobody messes with them. */ - at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */ - at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */ - at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */ - at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */ - at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */ - at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */ - at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */ - at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */ - at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */ - at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */ - at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */ - at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */ - at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */ - at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */ - at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */ - at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */ - at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */ + at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL); #ifdef CONFIG_BOARD_ATSTK1006 smc_set_timing(&nand_config, &nand_timing); diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c index 134b566630b..ac31666613a 100644 --- a/arch/avr32/boards/atstk1000/atstk1003.c +++ b/arch/avr32/boards/atstk1000/atstk1003.c @@ -131,23 +131,7 @@ static int __init atstk1003_init(void) * ATSTK1000 uses 32-bit SDRAM interface. Reserve the * SDRAM-specific pins so that nobody messes with them. */ - at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */ - at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */ - at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */ - at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */ - at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */ - at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */ - at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */ - at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */ - at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */ - at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */ - at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */ - at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */ - at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */ - at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */ - at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */ - at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */ - at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */ + at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL); #ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM at32_add_device_usart(1); diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c index ff8235a30ec..006a04e8bef 100644 --- a/arch/avr32/boards/favr-32/setup.c +++ b/arch/avr32/boards/favr-32/setup.c @@ -307,23 +307,7 @@ static int __init favr32_init(void) * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific * pins so that nobody messes with them. */ - at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */ - at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */ - at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */ - at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */ - at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */ - at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */ - at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */ - at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */ - at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */ - at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */ - at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */ - at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */ - at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */ - at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */ - at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */ - at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */ - at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */ + at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL); at32_select_gpio(GPIO_PIN_PB(3), 0); /* IRQ from ADS7843 */ diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h index a77d372f6f3..5c4c971eed8 100644 --- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h +++ b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h @@ -211,4 +211,7 @@ #define ATMEL_LCDC_ALT_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA) +/* Bitmask for all EBI data (D16..D31) pins on port E */ +#define ATMEL_EBI_PE_DATA_ALL (0x0000FFFF) + #endif /* __ASM_ARCH_AT32AP700X_H__ */ diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h index 21c79373b53..4873024e3b9 100644 --- a/arch/avr32/mach-at32ap/include/mach/portmux.h +++ b/arch/avr32/mach-at32ap/include/mach/portmux.h @@ -25,6 +25,6 @@ void at32_select_periph(unsigned int port, unsigned int pin, unsigned int periph, unsigned long flags); void at32_select_gpio(unsigned int pin, unsigned long flags); void at32_deselect_pin(unsigned int pin); -void at32_reserve_pin(unsigned int pin); +void at32_reserve_pin(unsigned int port, u32 pin_mask); #endif /* __ASM_ARCH_PORTMUX_H__ */ diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c index ed81a8bcb22..09a274c9d0b 100644 --- a/arch/avr32/mach-at32ap/pio.c +++ b/arch/avr32/mach-at32ap/pio.c @@ -167,22 +167,29 @@ void at32_deselect_pin(unsigned int pin) } /* Reserve a pin, preventing anyone else from changing its configuration. */ -void __init at32_reserve_pin(unsigned int pin) +void __init at32_reserve_pin(unsigned int port, u32 pin_mask) { struct pio_device *pio; - unsigned int pin_index = pin & 0x1f; - pio = gpio_to_pio(pin); + /* assign and verify pio */ + pio = gpio_to_pio(port); if (unlikely(!pio)) { - printk("pio: invalid pin %u\n", pin); + printk(KERN_WARNING "pio: invalid port %u\n", port); goto fail; } - if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) { - printk("%s: pin %u is busy\n", pio->name, pin_index); + /* Test if any of the requested pins is already muxed */ + spin_lock(&pio_lock); + if (unlikely(pio->pinmux_mask & pin_mask)) { + printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n", + pio->name, pin_mask, pio->pinmux_mask & pin_mask); + spin_unlock(&pio_lock); goto fail; } + /* Reserve pins */ + pio->pinmux_mask |= pin_mask; + spin_unlock(&pio_lock); return; fail: -- cgit v1.2.3 From dd5e1339e528197abdb7827663ff0673797fa088 Mon Sep 17 00:00:00 2001 From: Alex Raimondi Date: Tue, 9 Dec 2008 16:17:13 +0100 Subject: avr32: Hammerhead board support The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. This patch does include the basic support for the fpga device driver, but not the device driver itself. Signed-off-by: Alex Raimondi Signed-off-by: Haavard Skinnemoen --- arch/avr32/Kconfig | 19 + arch/avr32/Makefile | 1 + arch/avr32/boards/hammerhead/Kconfig | 43 + arch/avr32/boards/hammerhead/Makefile | 1 + arch/avr32/boards/hammerhead/flash.c | 377 ++++++++ arch/avr32/boards/hammerhead/flash.h | 6 + arch/avr32/boards/hammerhead/setup.c | 236 +++++ arch/avr32/configs/hammerhead_defconfig | 1467 +++++++++++++++++++++++++++++++ arch/avr32/mach-at32ap/at32ap700x.c | 4 +- arch/avr32/mach-at32ap/clock.h | 3 + 10 files changed, 2155 insertions(+), 2 deletions(-) create mode 100644 arch/avr32/boards/hammerhead/Kconfig create mode 100644 arch/avr32/boards/hammerhead/Makefile create mode 100644 arch/avr32/boards/hammerhead/flash.c create mode 100644 arch/avr32/boards/hammerhead/flash.h create mode 100644 arch/avr32/boards/hammerhead/setup.c create mode 100644 arch/avr32/configs/hammerhead_defconfig (limited to 'arch/avr32') diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 26eca87f673..b189680d18b 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -122,6 +122,24 @@ config BOARD_ATNGW100 bool "ATNGW100 Network Gateway" select CPU_AT32AP7000 +config BOARD_HAMMERHEAD + bool "Hammerhead board" + select CPU_AT32AP7000 + select USB_ARCH_HAS_HCD + help + The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. + It offers versatile peripherals, such as ethernet, usb device, usb host etc. + + The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered + Device (PD). + + Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is + mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which + will cover even the most exceptional need of memory bandwidth. Together with the onboard + video decoder the board is ready for video processing. + + For more information see: http://www.miromico.com/hammerhead + config BOARD_FAVR_32 bool "Favr-32 LCD-board" select CPU_AT32AP7000 @@ -133,6 +151,7 @@ endchoice source "arch/avr32/boards/atstk1000/Kconfig" source "arch/avr32/boards/atngw100/Kconfig" +source "arch/avr32/boards/hammerhead/Kconfig" source "arch/avr32/boards/favr-32/Kconfig" choice diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile index b088e103e75..f3ef3bbf797 100644 --- a/arch/avr32/Makefile +++ b/arch/avr32/Makefile @@ -33,6 +33,7 @@ head-y += arch/avr32/kernel/head.o core-y += $(machdirs) core-$(CONFIG_BOARD_ATSTK1000) += arch/avr32/boards/atstk1000/ core-$(CONFIG_BOARD_ATNGW100) += arch/avr32/boards/atngw100/ +core-$(CONFIG_BOARD_HAMMERHEAD) += arch/avr32/boards/hammerhead/ core-$(CONFIG_BOARD_FAVR_32) += arch/avr32/boards/favr-32/ core-$(CONFIG_BOARD_MIMC200) += arch/avr32/boards/mimc200/ core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/ diff --git a/arch/avr32/boards/hammerhead/Kconfig b/arch/avr32/boards/hammerhead/Kconfig new file mode 100644 index 00000000000..fda2331f978 --- /dev/null +++ b/arch/avr32/boards/hammerhead/Kconfig @@ -0,0 +1,43 @@ +# Hammerhead customization + +if BOARD_HAMMERHEAD + +config BOARD_HAMMERHEAD_USB + bool "Philips ISP116x-hcd USB support" + help + This enables USB support for Hammerheads internal ISP116x + controller from Philips. + + Choose 'Y' here if you want to have your board USB driven. + +config BOARD_HAMMERHEAD_LCD + bool "Atmel AT91/AT32 LCD support" + help + This enables LCD support for the Hammerhead board. You may + also add support for framebuffer devices (AT91/AT32 LCD Controller) + and framebuffer console support to get the most out of your LCD. + + Choose 'Y' here if you have ordered a Corona daugther board and + want to have support for your Hantronix HDA-351T-LV LCD. + +config BOARD_HAMMERHEAD_SND + bool "Atmel AC97 Sound support" + help + This enables Sound support for the Hammerhead board. You may + also go trough the ALSA settings to get it working. + + Choose 'Y' here if you have ordered a Corona daugther board and + want to make your board funky. + +config BOARD_HAMMERHEAD_FPGA + bool "Hammerhead FPGA Support" + default y + help + This adds support for the Cyclone III FPGA from Altera + found on Miromico's Hammerhead board. + + Choose 'Y' here if you want to have FPGA support enabled. + You will have to choose the "Hammerhead FPGA Device Support" in + Device Drivers->Misc to be able to use FPGA functionality. + +endif # BOARD_ATNGW100 diff --git a/arch/avr32/boards/hammerhead/Makefile b/arch/avr32/boards/hammerhead/Makefile new file mode 100644 index 00000000000..c740aa11675 --- /dev/null +++ b/arch/avr32/boards/hammerhead/Makefile @@ -0,0 +1 @@ +obj-y += setup.o flash.o diff --git a/arch/avr32/boards/hammerhead/flash.c b/arch/avr32/boards/hammerhead/flash.c new file mode 100644 index 00000000000..a98c6dd3a02 --- /dev/null +++ b/arch/avr32/boards/hammerhead/flash.c @@ -0,0 +1,377 @@ +/* + * Hammerhead board-specific flash initialization + * + * Copyright (C) 2008 Miromico AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../../mach-at32ap/clock.h" +#include "flash.h" + + +#define HAMMERHEAD_USB_PERIPH_GCLK0 0x40000000 +#define HAMMERHEAD_USB_PERIPH_CS2 0x02000000 +#define HAMMERHEAD_USB_PERIPH_EXTINT0 0x02000000 + +#define HAMMERHEAD_FPGA_PERIPH_MOSI 0x00000002 +#define HAMMERHEAD_FPGA_PERIPH_SCK 0x00000020 +#define HAMMERHEAD_FPGA_PERIPH_EXTINT3 0x10000000 + +static struct smc_timing flash_timing __initdata = { + .ncs_read_setup = 0, + .nrd_setup = 40, + .ncs_write_setup = 0, + .nwe_setup = 10, + + .ncs_read_pulse = 80, + .nrd_pulse = 40, + .ncs_write_pulse = 65, + .nwe_pulse = 55, + + .read_cycle = 120, + .write_cycle = 120, +}; + +static struct smc_config flash_config __initdata = { + .bus_width = 2, + .nrd_controlled = 1, + .nwe_controlled = 1, + .byte_write = 1, +}; + +static struct mtd_partition flash_parts[] = { + { + .name = "u-boot", + .offset = 0x00000000, + .size = 0x00020000, /* 128 KiB */ + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "root", + .offset = 0x00020000, + .size = 0x007d0000, + }, + { + .name = "env", + .offset = 0x007f0000, + .size = 0x00010000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(flash_parts), + .parts = flash_parts, +}; + +static struct resource flash_resource = { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = 0, + .resource = &flash_resource, + .num_resources = 1, + .dev = { .platform_data = &flash_data, }, +}; + +#ifdef CONFIG_BOARD_HAMMERHEAD_USB + +static struct smc_timing isp1160_timing __initdata = { + .ncs_read_setup = 75, + .nrd_setup = 75, + .ncs_write_setup = 75, + .nwe_setup = 75, + + + /* We use conservative timing settings, as the minimal settings aren't + stable. There may be room for tweaking. */ + .ncs_read_pulse = 75, /* min. 33ns */ + .nrd_pulse = 75, /* min. 33ns */ + .ncs_write_pulse = 75, /* min. 26ns */ + .nwe_pulse = 75, /* min. 26ns */ + + .read_cycle = 225, /* min. 143ns */ + .write_cycle = 225, /* min. 136ns */ +}; + +static struct smc_config isp1160_config __initdata = { + .bus_width = 2, + .nrd_controlled = 1, + .nwe_controlled = 1, + .byte_write = 0, +}; + +/* + * The platform delay function is only used to enforce the strange + * read to write delay. This can not be configured in the SMC. All other + * timings are controlled by the SMC (see timings obove) + * So in isp116x-hcd.c we should comment out USE_PLATFORM_DELAY + */ +void isp116x_delay(struct device *dev, int delay) +{ + if (delay > 150) + ndelay(delay - 150); +} + +static struct isp116x_platform_data isp1160_data = { + .sel15Kres = 1, /* use internal downstream resistors */ + .oc_enable = 0, /* external overcurrent detection */ + .int_edge_triggered = 0, /* interrupt is level triggered */ + .int_act_high = 0, /* interrupt is active low */ + .delay = isp116x_delay, /* platform delay function */ +}; + +static struct resource isp1160_resource[] = { + { + .start = 0x08000000, + .end = 0x08000001, + .flags = IORESOURCE_MEM, + }, + { + .start = 0x08000002, + .end = 0x08000003, + .flags = IORESOURCE_MEM, + }, + { + .start = 64, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device isp1160_device = { + .name = "isp116x-hcd", + .id = 0, + .resource = isp1160_resource, + .num_resources = 3, + .dev = { + .platform_data = &isp1160_data, + }, +}; +#endif + +#ifdef CONFIG_BOARD_HAMMERHEAD_USB +static int __init hammerhead_usbh_init(void) +{ + struct clk *gclk; + struct clk *osc; + + int ret; + + /* setup smc for usbh */ + smc_set_timing(&isp1160_config, &isp1160_timing); + ret = smc_set_configuration(2, &isp1160_config); + + if (ret < 0) { + printk(KERN_ERR + "hammerhead: failed to set ISP1160 USBH timing\n"); + return ret; + } + + /* setup gclk0 to run from osc1 */ + gclk = clk_get(NULL, "gclk0"); + if (IS_ERR(gclk)) + goto err_gclk; + + osc = clk_get(NULL, "osc1"); + if (IS_ERR(osc)) + goto err_osc; + + if (clk_set_parent(gclk, osc)) { + pr_debug("hammerhead: failed to set osc1 for USBH clock\n"); + goto err_set_clk; + } + + /* set clock to 6MHz */ + clk_set_rate(gclk, 6000000); + + /* and enable */ + clk_enable(gclk); + + /* select GCLK0 peripheral function */ + at32_select_periph(GPIO_PIOA_BASE, HAMMERHEAD_USB_PERIPH_GCLK0, + GPIO_PERIPH_A, 0); + + /* enable CS2 peripheral function */ + at32_select_periph(GPIO_PIOE_BASE, HAMMERHEAD_USB_PERIPH_CS2, + GPIO_PERIPH_A, 0); + + /* H_WAKEUP must be driven low */ + at32_select_gpio(GPIO_PIN_PA(8), AT32_GPIOF_OUTPUT); + + /* Select EXTINT0 for PB25 */ + at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_USB_PERIPH_EXTINT0, + GPIO_PERIPH_A, 0); + + /* register usbh device driver */ + platform_device_register(&isp1160_device); + + err_set_clk: + clk_put(osc); + err_osc: + clk_put(gclk); + err_gclk: + return ret; +} +#endif + +#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA +static struct smc_timing fpga_timing __initdata = { + .ncs_read_setup = 16, + .nrd_setup = 32, + .ncs_read_pulse = 48, + .nrd_pulse = 32, + .read_cycle = 64, + + .ncs_write_setup = 16, + .nwe_setup = 16, + .ncs_write_pulse = 32, + .nwe_pulse = 32, + .write_cycle = 64, +}; + +static struct smc_config fpga_config __initdata = { + .bus_width = 4, + .nrd_controlled = 1, + .nwe_controlled = 1, + .byte_write = 0, +}; + +static struct resource hh_fpga0_resource[] = { + { + .start = 0xffe00400, + .end = 0xffe00400 + 0x3ff, + .flags = IORESOURCE_MEM, + }, + { + .start = 4, + .end = 4, + .flags = IORESOURCE_IRQ, + }, + { + .start = 0x0c000000, + .end = 0x0c000100, + .flags = IORESOURCE_MEM, + }, + { + .start = 67, + .end = 67, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 hh_fpga0_dma_mask = DMA_32BIT_MASK; +static struct platform_device hh_fpga0_device = { + .name = "hh_fpga", + .id = 0, + .dev = { + .dma_mask = &hh_fpga0_dma_mask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .resource = hh_fpga0_resource, + .num_resources = ARRAY_SIZE(hh_fpga0_resource), +}; + +static struct clk hh_fpga0_spi_clk = { + .name = "spi_clk", + .dev = &hh_fpga0_device.dev, + .mode = pba_clk_mode, + .get_rate = pba_clk_get_rate, + .index = 1, +}; + +struct platform_device *__init at32_add_device_hh_fpga(void) +{ + /* Select peripheral functionallity for SPI SCK and MOSI */ + at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_SCK, + GPIO_PERIPH_B, 0); + at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_MOSI, + GPIO_PERIPH_B, 0); + + /* reserve all other needed gpio + * We have on board pull ups, so there is no need + * to enable gpio pull ups */ + /* INIT_DONE (input) */ + at32_select_gpio(GPIO_PIN_PB(0), 0); + + /* nSTATUS (input) */ + at32_select_gpio(GPIO_PIN_PB(2), 0); + + /* nCONFIG (output, low) */ + at32_select_gpio(GPIO_PIN_PB(3), AT32_GPIOF_OUTPUT); + + /* CONF_DONE (input) */ + at32_select_gpio(GPIO_PIN_PB(4), 0); + + /* Select EXTINT3 for PB28 (Interrupt from FPGA) */ + at32_select_periph(GPIO_PIOB_BASE, HAMMERHEAD_FPGA_PERIPH_EXTINT3, + GPIO_PERIPH_A, 0); + + /* Get our parent clock */ + hh_fpga0_spi_clk.parent = clk_get(NULL, "pba"); + clk_put(hh_fpga0_spi_clk.parent); + + /* Register clock in at32 clock tree */ + at32_clk_register(&hh_fpga0_spi_clk); + + platform_device_register(&hh_fpga0_device); + return &hh_fpga0_device; +} +#endif + +/* This needs to be called after the SMC has been initialized */ +static int __init hammerhead_flash_init(void) +{ + int ret; + + smc_set_timing(&flash_config, &flash_timing); + ret = smc_set_configuration(0, &flash_config); + + if (ret < 0) { + printk(KERN_ERR "hammerhead: failed to set NOR flash timing\n"); + return ret; + } + + platform_device_register(&flash_device); + +#ifdef CONFIG_BOARD_HAMMERHEAD_USB + hammerhead_usbh_init(); +#endif + +#ifdef CONFIG_BOARD_HAMMERHEAD_FPGA + /* Setup SMC for FPGA interface */ + smc_set_timing(&fpga_config, &fpga_timing); + ret = smc_set_configuration(3, &fpga_config); +#endif + + + if (ret < 0) { + printk(KERN_ERR "hammerhead: failed to set FPGA timing\n"); + return ret; + } + + return 0; +} + +device_initcall(hammerhead_flash_init); diff --git a/arch/avr32/boards/hammerhead/flash.h b/arch/avr32/boards/hammerhead/flash.h new file mode 100644 index 00000000000..ea70c626587 --- /dev/null +++ b/arch/avr32/boards/hammerhead/flash.h @@ -0,0 +1,6 @@ +#ifndef __BOARDS_HAMMERHEAD_FLASH_H +#define __BOARDS_HAMMERHEAD_FLASH_H + +struct platform_device *at32_add_device_hh_fpga(void); + +#endif /* __BOARDS_HAMMERHEAD_FLASH_H */ diff --git a/arch/avr32/boards/hammerhead/setup.c b/arch/avr32/boards/hammerhead/setup.c new file mode 100644 index 00000000000..af45c26c5ff --- /dev/null +++ b/arch/avr32/boards/hammerhead/setup.c @@ -0,0 +1,236 @@ +/* + * Board-specific setup code for the Miromico Hammerhead board + * + * Copyright (C) 2008 Miromico AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include