From f099f39acf7575eff3dee3c562cec4e592876c33 Mon Sep 17 00:00:00 2001
From: Sonic Zhang <sonic.zhang@analog.com>
Date: Thu, 9 Oct 2008 14:11:57 +0800
Subject: Blackfin arch: Make L2 SRAM cacheable

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
---
 arch/blackfin/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'arch/blackfin/Kconfig')

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 554ac5827c1..10c97efbd91 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -772,6 +772,13 @@ config BFIN_WT
 
 endchoice
 
+config BFIN_L2_CACHEABLE
+	bool "Cache L2 SRAM"
+	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+	default n
+	help
+	  Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
 config MPU
 	bool "Enable the memory protection unit (EXPERIMENTAL)"
 	default n
-- 
cgit v1.2.3