From 639f6571458948b5112be2cf00c0c2c04db2897d Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Wed, 27 Aug 2008 10:51:02 +0800 Subject: Blackfin arch: move include/asm-blackfin header files to arch/blackfin Signed-off-by: Bryan Wu --- arch/blackfin/include/asm/time.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/blackfin/include/asm/time.h (limited to 'arch/blackfin/include/asm/time.h') diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h new file mode 100644 index 00000000000..ddc43ce3853 --- /dev/null +++ b/arch/blackfin/include/asm/time.h @@ -0,0 +1,40 @@ +/* + * asm-blackfin/time.h: + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIME_H +#define _ASM_BLACKFIN_TIME_H + +/* + * The way that the Blackfin core timer works is: + * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) + * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) + * + * If you take the fastest clock (1ns, or 1GHz to make the math work easier) + * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter + * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need + * to use TSCALE, and program it to zero (which is pass CCLK through). + * If you feel like using it, try to keep HZ * TIMESCALE to some + * value that divides easy (like power of 2). + */ + +#ifndef CONFIG_CPU_FREQ +#define TIME_SCALE 1 +#define __bfin_cycles_off (0) +#define __bfin_cycles_mod (0) +#else +/* + * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . + * Whenever we change the Core Clock frequency changes we immediately + * adjust the Core Timer Presale Register. This way we don't lose time. + */ +#define TIME_SCALE 4 +extern unsigned long long __bfin_cycles_off; +extern unsigned int __bfin_cycles_mod; +#endif + +#endif -- cgit v1.2.3