From cb15e57cc7d68e524f709c9a541b4900df80df16 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 18 Nov 2008 17:48:22 +0800 Subject: Blackfin arch: noMMU CPLB lookup tables can be in L1 SRAM - unify duplicate page_size_table definitions - make sure it is placed alongside the other cplb switching code Pointed-out-by: Michael McTernan Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/kernel/cplbinfo.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'arch/blackfin/kernel/cplbinfo.c') diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c index dc584fe18e5..723839da14a 100644 --- a/arch/blackfin/kernel/cplbinfo.c +++ b/arch/blackfin/kernel/cplbinfo.c @@ -59,12 +59,7 @@ static char *cplb_print_entry(char *buf, cplb_type type, unsigned int cpu) #else -static int page_size_table[4] = { - 0x00000400, /* 1K */ - 0x00001000, /* 4K */ - 0x00100000, /* 1M */ - 0x00400000 /* 4M */ -}; +extern int page_size_table[]; static int cplb_find_entry(unsigned long *cplb_addr, unsigned long *cplb_data, unsigned long addr, -- cgit v1.2.3