From b85b82d980526d683dc3b39f2ac1f447fa84a105 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 24 Apr 2008 06:13:37 +0800 Subject: [Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978 Section data_l1_cacheline_aligned should be defined in link script of kernel, when L1 data sram bank A is not available. In bf536 with all data cache is enabled, there is no L1 data sram. Current link script won't define section data_l1.cacheline_aligned in this case. But, if user select put cacheline_aligned data into l1 sram in kernel menuconfig, these data will be dropped and access to these data will trigger data CPLB exception. Do panic in l1 relocation code as well. Signed-off-by: Sonic Zhang Signed-off-by: Bryan Wu --- arch/blackfin/kernel/vmlinux.lds.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/blackfin/kernel/vmlinux.lds.S') diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 7a1200328ac..288dfdbfb61 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S @@ -83,6 +83,11 @@ SECTIONS . = ALIGN(32); *(.data.cacheline_aligned) +#if !L1_DATA_A_LENGTH + . = ALIGN(32); + *(.data_l1.cacheline_aligned) +#endif + DATA_DATA *(.data.*) CONSTRUCTORS -- cgit v1.2.3