From 976119bc5d2253bb47f3255ee178ce1ee605fd3c Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Wed, 1 Jul 2009 07:05:40 +0000 Subject: Blackfin: update anomaly lists to match latest sheets/usage Signed-off-by: Graf Yang Signed-off-by: Cliff Cai Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf561/include/mach/anomaly.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/blackfin/mach-bf561/include') diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 94b8e277f09..a5312b2d267 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -288,6 +288,7 @@ #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) -- cgit v1.2.3 From fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 29 Jun 2009 14:20:10 -0400 Subject: Blackfin: handle BF561 Core B memory regions better when SMP=n Rather than assume Core B is always run with caches turned on, let people load into any of the on-chip memory regions. It is their business how the SRAM/Cache regions are utilized, so don't prevent them from being able to load into them. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf561/include/mach/mem_map.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/mach-bf561/include') diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index a63e15c86d9..5b96ea549a0 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -37,7 +37,6 @@ /* Memory Map for ADSP-BF561 processors */ -#ifdef CONFIG_BF561 #define COREA_L1_CODE_START 0xFFA00000 #define COREA_L1_DATA_A_START 0xFF800000 #define COREA_L1_DATA_B_START 0xFF900000 @@ -74,6 +73,28 @@ #define BFIN_DCACHESIZE (0*1024) #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ + +/* + * If we are in SMP mode, then the cache settings of Core B will match + * the settings of Core A. If we aren't, then we assume Core B is not + * using any cache. This allows the rest of the kernel to work with + * the core in either mode as we are only loading user code into it and + * it is the user's problem to make sure they aren't doing something + * stupid there. + * + * Note that we treat the L1 code region as a contiguous blob to make + * the rest of the kernel simpler. Easier to check one region than a + * bunch of small ones. Again, possible misbehavior here is the fault + * of the user -- don't try to use memory that doesn't exist. + */ +#ifdef CONFIG_SMP +# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH +# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH +# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH +#else +# define COREB_L1_CODE_LENGTH 0x14000 +# define COREB_L1_DATA_A_LENGTH 0x8000 +# define COREB_L1_DATA_B_LENGTH 0x8000 #endif /* Level 2 Memory */ -- cgit v1.2.3 From f1c717fbf89f5a24d539ecf4baa5d4c3888e3bf9 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 1 Jul 2009 07:43:23 +0000 Subject: Blackfin: fix wrong CTS inversion The Blackfin serial headers were inverting the CTS value leading to wrong handling of the CTS line which broke CTS/RTS handling completely. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/blackfin/mach-bf561/include') diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h index a1b50878553..fd5e8878b8c 100644 --- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h @@ -53,7 +53,7 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) -#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) +#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) -- cgit v1.2.3