From fedb25fae72bc2c3709448a43be067439643da87 Mon Sep 17 00:00:00 2001 From: "Chen, Kenneth W" Date: Thu, 17 Nov 2005 01:38:42 -0800 Subject: [IA64] 4 level page table bug fix in vhpt_miss From source code inspection, I think there is a bug with 4 level page table with vhpt_miss handler. In the code path of rechecking page table entry against previously read value after tlb insertion, *pte value in register r18 was overwritten with value newly read from pud pointer, render the check of new *pte against previous *pte completely wrong. Though the bug is none fatal and the penalty is to purge the entry and retry. For functional correctness, it should be fixed. The fix is to use a different register so new *pud don't trash *pte. (btw, the comments in the cmp statement is wrong as well, which I will address in the next patch). Signed-off-by: Ken Chen Signed-off-by: Tony Luck --- arch/ia64/kernel/ivt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/ia64') diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S index e06f21f60dc..c71c79262a4 100644 --- a/arch/ia64/kernel/ivt.S +++ b/arch/ia64/kernel/ivt.S @@ -209,13 +209,13 @@ ENTRY(vhpt_miss) ld8 r25=[r21] // read L4 entry again ld8 r26=[r17] // read L3 PTE again #ifdef CONFIG_PGTABLE_4 - ld8 r18=[r28] // read L2 entry again + ld8 r19=[r28] // read L2 entry again #endif cmp.ne p6,p7=r0,r0 ;; cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change #ifdef CONFIG_PGTABLE_4 - cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change + cmp.ne.or.andcm p6,p7=r19,r29 // did L4 PTE change #endif mov r27=PAGE_SHIFT<<2 ;; -- cgit v1.2.3