From 24a1836ecd471409aeb5362f63032126ebe7fb10 Mon Sep 17 00:00:00 2001 From: "sfking@fdwdc.com" Date: Fri, 19 Jun 2009 18:11:02 -0700 Subject: generic GPIO support for the Freescale Coldire 5206e. Add support for the 5206e. Signed-off-by: Steven King Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/5206e/config.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/m68knommu/platform/5206e/config.c') diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index 65887799db8..fcf1400db51 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 5187995f0a9253e915dfee83684eae7b692213e6 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 19 May 2009 14:08:47 +1000 Subject: m68knommu: remove duplicate ColdFire mcf_autovector() code Each of the ColdFire CPU platform code that used the old style interrupt controller had its own copy of the mcf_autovector() function. They are all the same, remove them all and create a single function in the common coldfire/intc.c code. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/5206e/config.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'arch/m68knommu/platform/5206e/config.c') diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index fcf1400db51..29e565a4443 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c @@ -69,23 +69,6 @@ static void __init m5206e_uarts_init(void) /***************************************************************************/ -void mcf_autovector(unsigned int vec) -{ - volatile unsigned char *mbar; - unsigned char icr; - - if ((vec >= 25) && (vec <= 31)) { - vec -= 25; - mbar = (volatile unsigned char *) MCF_MBAR; - icr = MCFSIM_ICR_AUTOVEC | (vec << 3); - *(mbar + MCFSIM_ICR1 + vec) = icr; - vec = 0x1 << (vec + 1); - mcf_setimr(mcf_getimr() & ~vec); - } -} - -/***************************************************************************/ - void mcf_settimericr(unsigned int timer, unsigned int level) { volatile unsigned char *icrp; -- cgit v1.2.3 From f2154bef817ac3d0ea67b52526fd8e88898b66f9 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 19 May 2009 14:38:08 +1000 Subject: m68knommu: merge old ColdFire interrupt controller masking macros Currently the code that supports setting the old style ColdFire interrupt controller mask registers is macros in the include files of each of the CPU types. Merge all these into a set of real masking functions in the old Coldfire interrupt controller code proper. All the macros are basically the same (excepting a register size difference on really early parts). Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/5206e/config.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch/m68knommu/platform/5206e/config.c') diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index 29e565a4443..08ef7e26898 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c @@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq) if (line == 0) { writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); + mcf_clrimr(MCFINTC_UART0); } else if (line == 1) { writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); + mcf_clrimr(MCFINTC_UART1); } } @@ -76,13 +76,13 @@ void mcf_settimericr(unsigned int timer, unsigned int level) if (timer <= 2) { switch (timer) { - case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; - default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; + case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; + default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; } icrp = (volatile unsigned char *) (MCF_MBAR + icr); *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; - mcf_setimr(mcf_getimr() & ~imr); + mcf_clrimr(imr); } } @@ -101,8 +101,6 @@ void m5206e_cpu_reset(void) void __init config_BSP(char *commandp, int size) { - mcf_setimr(MCFSIM_IMR_MASKALL); - #if defined(CONFIG_NETtel) /* Copy command line from FLASH to local buffer... */ memcpy(commandp, (char *) 0xf0004000, size); -- cgit v1.2.3 From 04b75b10dceadf937e3707ecc3dfccf6a076fd29 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 19 May 2009 14:52:40 +1000 Subject: m68knommu: simplify ColdFire "timers" clock initialization The ColdFire "timers" clock setup can be simplified. There is really no need for the flexible per-platform setup code. The clock interrupt can be hard defined per CPU platform (in CPU include files). This makes the actual timer code simpler. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/5206e/config.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'arch/m68knommu/platform/5206e/config.c') diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index 08ef7e26898..363296af2ee 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c @@ -69,21 +69,17 @@ static void __init m5206e_uarts_init(void) /***************************************************************************/ -void mcf_settimericr(unsigned int timer, unsigned int level) +static void __init m5206e_timers_init(void) { - volatile unsigned char *icrp; - unsigned int icr, imr; - - if (timer <= 2) { - switch (timer) { - case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break; - default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break; - } - - icrp = (volatile unsigned char *) (MCF_MBAR + icr); - *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; - mcf_clrimr(imr); - } + /* Timer1 is always used as system timer */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, + MCF_MBAR + MCFSIM_TIMER1ICR); + +#ifdef CONFIG_HIGHPROFILE + /* Timer2 is to be used as a high speed profile timer */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, + MCF_MBAR + MCFSIM_TIMER2ICR); +#endif } /***************************************************************************/ @@ -108,6 +104,7 @@ void __init config_BSP(char *commandp, int size) #endif /* CONFIG_NETtel */ mach_reset = m5206e_cpu_reset; + m5206e_timers_init(); } /***************************************************************************/ -- cgit v1.2.3 From 39f0fb6a3448cfc316e0d5295ed1b121db50037e Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 22 May 2009 13:33:35 +1000 Subject: m68knommu: map ColdFire interrupts to correct masking bits The older simple ColdFire interrupt controller has no one-to-one mapping of interrupt numbers to bits in the interrupt mask register. Create a mapping array that each ColdFire CPU type can populate with its available interrupts and the bits that each use in the interrupt mask register. Signed-off-by: Greg Ungerer --- arch/m68knommu/platform/5206e/config.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/m68knommu/platform/5206e/config.c') diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index 363296af2ee..0f41ba82a3b 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c @@ -50,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq) if (line == 0) { writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); - mcf_clrimr(MCFINTC_UART0); + mcf_mapirq2imr(irq, MCFINTC_UART0); } else if (line == 1) { writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); - mcf_clrimr(MCFINTC_UART1); + mcf_mapirq2imr(irq, MCFINTC_UART1); } } @@ -74,11 +74,13 @@ static void __init m5206e_timers_init(void) /* Timer1 is always used as system timer */ writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, MCF_MBAR + MCFSIM_TIMER1ICR); + mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); #ifdef CONFIG_HIGHPROFILE /* Timer2 is to be used as a high speed profile timer */ writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, MCF_MBAR + MCFSIM_TIMER2ICR); + mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); #endif } @@ -105,13 +107,18 @@ void __init config_BSP(char *commandp, int size) mach_reset = m5206e_cpu_reset; m5206e_timers_init(); + m5206e_uarts_init(); + + /* Only support the external interrupts on their primary level */ + mcf_mapirq2imr(25, MCFINTC_EINT1); + mcf_mapirq2imr(28, MCFINTC_EINT4); + mcf_mapirq2imr(31, MCFINTC_EINT7); } /***************************************************************************/ static int __init init_BSP(void) { - m5206e_uarts_init(); platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); return 0; } -- cgit v1.2.3