From 82622284dd2f8791f9759f3cef601520a8bc63b2 Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 14 Oct 2009 12:16:56 -0700 Subject: MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f6f3b990d83..20b223ba654 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1427,6 +1427,9 @@ config CPU_SUPPORTS_64BIT_KERNEL bool config CPU_SUPPORTS_HUGEPAGES bool +config MIPS_PGD_C0_CONTEXT + bool + default y if 64BIT && CPU_MIPSR2 # # Set to y for ptrace access to watch registers. -- cgit v1.2.3