From 9247857f5acadf0ea87fd6a9514c633644634f08 Mon Sep 17 00:00:00 2001 From: "Mark.Zhan" Date: Tue, 20 Jun 2006 18:15:02 +0800 Subject: [MIPS] Fix the build error of Wind River PPMC board, rewrite irq code to C o Fix the build error Wind River PPMC board caused by the change of plat_setup hook interface. o Rewrite first level interrupt dispatch code to C. Signed-off-by: Rongkai.Zhan Signed-off-by: Ralf Baechle --- arch/mips/gt64120/wrppmc/Makefile | 2 +- arch/mips/gt64120/wrppmc/int-handler.S | 59 ---------------------------------- arch/mips/gt64120/wrppmc/irq.c | 17 +++++++--- arch/mips/gt64120/wrppmc/setup.c | 2 +- 4 files changed, 15 insertions(+), 65 deletions(-) delete mode 100644 arch/mips/gt64120/wrppmc/int-handler.S (limited to 'arch/mips/gt64120') diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index 72606b9af12..7cf52205511 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile @@ -9,6 +9,6 @@ # Makefile for the Wind River MIPS 4KC PPMC Eval Board # -obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o +obj-y += irq.o reset.o setup.o time.o pci.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S deleted file mode 100644 index edee7b39417..00000000000 --- a/arch/mips/gt64120/wrppmc/int-handler.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle - * Copyright (C) Wind River System Inc. Rongkai.Zhan - */ -#include -#include -#include -#include -#include -#include - - .align 5 - .set noat -NESTED(handle_IRQ, PT_SIZE, sp) - SAVE_ALL - CLI # Important: mark KERNEL mode ! - .set at - - mfc0 t0, CP0_CAUSE # get pending interrupts - mfc0 t1, CP0_STATUS # get enabled interrupts - and t0, t0, t1 # get allowed interrupts - andi t0, t0, 0xFF00 - beqz t0, 1f - move a1, sp # Prepare 'struct pt_regs *regs' pointer - - andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer - bnez t1, handle_cputimer_irq - andi t1, t0, CAUSEF_IP6 # UART 16550 port - bnez t1, handle_uart_irq - andi t1, t0, CAUSEF_IP3 # PCI INT_A - bnez t1, handle_pci_intA_irq - - /* wrong alarm or masked ... */ -1: j spurious_interrupt - nop -END(handle_IRQ) - - .align 5 -handle_cputimer_irq: - li a0, WRPPMC_MIPS_TIMER_IRQ - jal do_IRQ - j ret_from_irq - - .align 5 -handle_uart_irq: - li a0, WRPPMC_UART16550_IRQ - jal do_IRQ - j ret_from_irq - - .align 5 -handle_pci_intA_irq: - li a0, WRPPMC_PCI_INTA_IRQ - jal do_IRQ - j ret_from_irq - diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 8605687e24e..26cf360f169 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -30,7 +30,19 @@ #include #include -extern asmlinkage void handle_IRQ(void); +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP7) + do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */ + else if (pending & STATUSF_IP6) + do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */ + else if (pending & STATUSF_IP3) + do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */ + else + spurious_interrupt(regs); +} /** * Initialize GT64120 Interrupt Controller @@ -53,9 +65,6 @@ void __init arch_init_irq(void) /* enable all CPU interrupt bits. */ set_c0_status(ST0_IM); /* IE bit is still 0 */ - /* Install MIPS Interrupt Trap Vector */ - set_except_vector(0, handle_IRQ); - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ mips_cpu_irq_init(0); diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index 20c591e49da..2db6375ef29 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -125,7 +125,7 @@ static void wrppmc_setup_serial(void) } #endif -void __init plat_setup(void) +void __init plat_mem_setup(void) { extern void wrppmc_time_init(void); extern void wrppmc_timer_setup(struct irqaction *); -- cgit v1.2.3 From 0ef831b1ff1ff0bcd8bf5b1890913ef6bb263250 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 20 Jun 2006 21:33:02 +0900 Subject: [MIPS] Removes unused functions for GT64120 Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/gt64120/common/Makefile | 1 - arch/mips/gt64120/common/pci.c | 147 -------------------------------------- 2 files changed, 148 deletions(-) delete mode 100644 arch/mips/gt64120/common/pci.c (limited to 'arch/mips/gt64120') diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile index eba5051015a..1ef676e22ab 100644 --- a/arch/mips/gt64120/common/Makefile +++ b/arch/mips/gt64120/common/Makefile @@ -3,4 +3,3 @@ # obj-y += time.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c deleted file mode 100644 index e9e5419a0d5..00000000000 --- a/arch/mips/gt64120/common/pci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include - -#define SELF 0 - -/* - * pciXReadConfigReg - Read from a PCI configuration register - * - Make sure the GT is configured as a master before - * reading from another device on the PCI. - * - The function takes care of Big/Little endian conversion. - * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI - * spec) - * pciDevNum: The device number needs to be addressed. - * RETURNS: data , if the data == 0xffffffff check the master abort bit in the - * cause register to make sure the data is valid - * - * Configuration Address 0xCF8: - * - * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number - * |congif|Reserved| Bus |Device|Function|Register|00| - * |Enable| |Number|Number| Number | Number | | <=field Name - * - */ -static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - - /* - * The casual observer might wonder why the READ is duplicated here, - * rather than immediately following the WRITE, and just have the swap - * in the "if". That's because there is a latency problem with trying - * to read immediately after setting up the address register. The "if" - * check gives enough time for the address to stabilize, so the READ - * can work. - */ - if (PCI_SLOT(device->devfn) == SELF) /* This board */ - return GT_READ(GT_PCI0_CFGDATA_OFS); - else /* PCI is little endian so swap the Data. */ - return __GT_READ(GT_PCI0_CFGDATA_OFS); -} - -/* - * pciXWriteConfigReg - Write to a PCI configuration register - * - Make sure the GT is configured as a master before - * writingto another device on the PCI. - * - The function takes care of Big/Little endian conversion. - * Inputs: unsigned int regOffset: The register offset as it apears in the - * GT spec - * (or any other PCI device spec) - * pciDevNum: The device number needs to be addressed. - * - * Configuration Address 0xCF8: - * - * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number - * |congif|Reserved| Bus |Device|Function|Register|00| - * |Enable| |Number|Number| Number | Number | | <=field Name - * - */ -static void pci0WriteConfigReg(unsigned int offset, - struct pci_dev *device, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - - if (PCI_SLOT(device->devfn) == SELF) /* This board */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); - else /* configuration Transaction over the pci. */ - __GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -extern struct pci_ops gt64120_pci_ops; - -void __init pcibios_init(void) -{ - u32 tmp; - struct pci_dev controller; - - controller.devfn = SELF; - - tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ - tmp = GT_READ(GT_PCI0_BARE_OFS); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); - - /* - * Reset PCI I/O and PCI MEM values to ones supported by EVM. - */ - ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; - iomem_resource.start = GT_PCI_MEM_BASE; - iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1; - - pci_scan_bus(0, >64120_pci_ops, NULL); -} -- cgit v1.2.3 From 08aecfb9eaf019f07384175101c970ede271c17a Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 20 Jun 2006 23:26:30 +0900 Subject: [MIPS] Remove set_c0_status(ST0_IM) from wrppmc's irq.c. mips_cpu_irq_init() does clear_c0_status(ST0_IM) first, so set_c0_status(ST0_IM) isn't necessary. Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/gt64120/wrppmc/irq.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/mips/gt64120') diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 26cf360f169..8d75a43ce87 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -62,9 +62,6 @@ void gt64120_init_pic(void) void __init arch_init_irq(void) { - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0 */ - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ mips_cpu_irq_init(0); -- cgit v1.2.3 From 6feb6efaec9858dfb673fc5c89b8280b1b73bb08 Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 20 Jun 2006 23:55:17 +0900 Subject: [MIPS] Remove first timer interrupt setup in wrppmc_timer_setup() The first timer interrupt setup already happens in time_init(). Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle --- arch/mips/gt64120/wrppmc/time.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips/gt64120') diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 175d22adb45..6c24a82df0d 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -31,10 +31,6 @@ void __init wrppmc_timer_setup(struct irqaction *irq) { /* Install ISR for timer interrupt */ setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); - - /* to generate the first timer interrupt */ - write_c0_compare(mips_hpt_frequency/HZ); - write_c0_count(0); } /* -- cgit v1.2.3 From fc103349bb7d3f011ffe9678da86a35634f4b6fc Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 28 Jun 2006 11:24:12 +0100 Subject: [MIPS] Remove BSD and Sys V compat data types. Signed-off-by: Ralf Baechle --- arch/mips/gt64120/momenco_ocelot/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/gt64120') diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index 1193a22c469..9804642ecf8 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -164,8 +164,8 @@ void __init plat_mem_setup(void) pm_power_off = momenco_ocelot_power_off; /* - * initrd_start = (ulong)ocelot_initrd_start; - * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_start = (unsigned long)ocelot_initrd_start; + * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; * initrd_below_start_ok = 1; */ -- cgit v1.2.3