From 785e3268e2951d4c0c21417c8e5d8004b2ab2480 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:17 +0100 Subject: MIPS: Alchemy: update core interrupt code. This patch attempts to modernize core Alchemy interrupt handling code. - add irq_chips for irq controllers instead of irq type, - add a set_type() hook to change irq trigger type during runtime, - add a set_wake() hook to control GPIO0..7 based wakeup, - use linux' IRQF_TRIGGER_ constants instead of homebrew ones, - enable GENERIC_HARDIRQS_NO__DO_IRQ. - simplify plat_irq_dispatch - merge au1xxx_irqmap into irq.c file, the only place where its contents are referenced. - board_init_irq() is now mandatory for every board; use it to register the remaining (gpio-based) interrupt sources; update all boards accordingly. Run-tested on Db1200 and other Au1200 based platforms. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c --- arch/mips/include/asm/mach-au1x00/au1000.h | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 0d302bad449..a7ba35247c8 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -109,10 +109,11 @@ struct au1xxx_irqmap { int im_request; }; -/* - * init_IRQ looks for a table with this name. - */ -extern struct au1xxx_irqmap au1xxx_irq_map[]; +/* core calls this function to let boards initialize other IRQ sources */ +void board_init_irq(void); + +/* boards call this to register additional (GPIO) interrupts */ +void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); #endif /* !defined (_LANGUAGE_ASSEMBLY) */ @@ -505,15 +506,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; #define IC1_TESTBIT 0xB1800080 -/* Interrupt Configuration Modes */ -#define INTC_INT_DISABLED 0x0 -#define INTC_INT_RISE_EDGE 0x1 -#define INTC_INT_FALL_EDGE 0x2 -#define INTC_INT_RISE_AND_FALL_EDGE 0x3 -#define INTC_INT_HIGH_LEVEL 0x5 -#define INTC_INT_LOW_LEVEL 0x6 -#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 - /* Interrupt Numbers */ /* Au1000 */ #ifdef CONFIG_SOC_AU1000 -- cgit v1.2.3 From 1820ec1d2b993f3ec00169e881504aa4541a9bf7 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:20 +0100 Subject: MIPS: Alchemy: remove get/set_au1x00_lcd_clock(). There are no in-tree users, so remove them. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index a7ba35247c8..d07632e3230 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -97,8 +97,6 @@ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); -extern void set_au1x00_lcd_clock(void); -extern unsigned int get_au1x00_lcd_clock(void); /* * Every board describes its IRQ mapping with this table. -- cgit v1.2.3 From 074cf656700ddd1d2bd7f815f78e785418beb898 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:21 +0100 Subject: MIPS: Alchemy: remove cpu_table. Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle delete mode 100644 arch/mips/alchemy/common/cputable.c --- arch/mips/include/asm/mach-au1x00/au1000.h | 58 +++++++++++++++++++----------- 1 file changed, 38 insertions(+), 20 deletions(-) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index d07632e3230..5db26e60a8c 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -91,6 +91,44 @@ static inline u32 au_readl(unsigned long reg) return *(volatile u32 *)reg; } +/* Early Au1000 have a write-only SYS_CPUPLL register. */ +static inline int au1xxx_cpu_has_pll_wo(void) +{ + switch (read_c0_prid()) { + case 0x00030100: /* Au1000 DA */ + case 0x00030201: /* Au1000 HA */ + case 0x00030202: /* Au1000 HB */ + return 1; + } + return 0; +} + +/* does CPU need CONFIG[OD] set to fix tons of errata? */ +static inline int au1xxx_cpu_needs_config_od(void) +{ + /* + * c0_config.od (bit 19) was write only (and read as 0) on the + * early revisions of Alchemy SOCs. It disables the bus trans- + * action overlapping and needs to be set to fix various errata. + */ + switch (read_c0_prid()) { + case 0x00030100: /* Au1000 DA */ + case 0x00030201: /* Au1000 HA */ + case 0x00030202: /* Au1000 HB */ + case 0x01030200: /* Au1500 AB */ + /* + * Au1100/Au1200 errata actually keep silence about this bit, + * so we set it just in case for those revisions that require + * it to be set according to the (now gone) cpu_table. + */ + case 0x02030200: /* Au1100 AB */ + case 0x02030201: /* Au1100 BA */ + case 0x02030202: /* Au1100 BC */ + case 0x04030201: /* Au1200 AC */ + return 1; + } + return 0; +} /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); @@ -1739,24 +1777,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; #endif -/* - * Processor information based on PRID. - * Copied from PowerPC. - */ -#ifndef _LANGUAGE_ASSEMBLY -struct cpu_spec { - /* CPU is matched via (PRID & prid_mask) == prid_value */ - unsigned int prid_mask; - unsigned int prid_value; - - char *cpu_name; - unsigned char cpu_od; /* Set Config[OD] */ - unsigned char cpu_bclk; /* Enable BCLK switching */ - unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ -}; - -extern struct cpu_spec cpu_specs[]; -extern struct cpu_spec *cur_cpu_spec[]; -#endif - #endif -- cgit v1.2.3 From 2699cdfb765c3b7d77d28ea3bc7d84e486697177 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:24 +0100 Subject: MIPS: Alchemy: move calc_clock function. Now that nothing in time.c depends on calc_clock, it can be moved to clocks.c where it belongs. While at it, give it a better non-generic name and call it as soon as possible in plat_mem_init. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 5db26e60a8c..2b88c2982cb 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -135,6 +135,7 @@ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); +extern unsigned long au1xxx_calc_clock(void); /* * Every board describes its IRQ mapping with this table. -- cgit v1.2.3 From 564365b0fc3395ed55501ef25705664888cebdbc Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:25 +0100 Subject: MIPS: Alchemy: Fix up PM code on Au1550/Au1200 Au1550/Au1200 have a different memory controller which requires additi- onal code to properly put memory to sleep (code taken from AMD/RMI's Linux-2.6.11 source package). Also fix up the remaining pm-related paths to compile on Au1200/Au1550 platforms. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/au1000.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2b88c2982cb..515373c6d4a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -137,6 +137,12 @@ extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); extern unsigned long au1xxx_calc_clock(void); +/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ +void au1xxx_save_and_sleep(void); +void au_sleep(void); +void save_au1xxx_intctl(void); +void restore_au1xxx_intctl(void); + /* * Every board describes its IRQ mapping with this table. */ -- cgit v1.2.3 From 61f9c58da57a80b0df1ced18a28cbbaebd4d417a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Sun, 21 Dec 2008 09:26:27 +0100 Subject: MIPS: Alchemy: new userspace suspend interface for development boards. Replace the current sysctl-based suspend interface with a new sysfs- based one which also uses the Linux-2.6 suspend model. To configure wakeup sources, a subtree for the demoboards is created under /sys/power/db1x: sys/ `-- power `-- db1x |-- gpio0 |-- gpio1 |-- gpio2 |-- gpio3 |-- gpio4 |-- gpio5 |-- gpio6 |-- gpio7 |-- timer |-- timer_timeout |-- wakemsk `-- wakesrc The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2 bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1' enables a wakesource, 0 disables it. The 'timer_timeout' node holds the timeout in seconds after which the TOYMATCH2 event should wake the system. The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex), the 'wakemsk' node can be used to get/set the wakeup mask directly. For example, to have the timer wake the system after 10 seconds of sleep, the following must be done in userspace: echo 10 > /sys/power/db1x/timer_timeout echo 1 > /sys/power/db1x/timer echo mem > /sys/power/sleep This patch also removes the homebrew CPU frequency switching code. I don't understand how it could have ever worked reliably; it does not communicate the clock changes to peripheral devices other than uarts. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle create mode 100644 arch/mips/alchemy/devboards/pm.c --- arch/mips/include/asm/mach-au1x00/au1000.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h') diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 515373c6d4a..62f91f50b5b 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1560,6 +1560,10 @@ enum soc_au1200_ints { #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C +#define SYS_WAKEMSK_D2 (1 << 9) +#define SYS_WAKEMSK_M2 (1 << 8) +#define SYS_WAKEMSK_GPIO(x) (1 << (x)) + /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 # define SYS_FC_FRDIV2_BIT 22 -- cgit v1.2.3