From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- arch/mips/kernel/irq-msc01.c | 189 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 arch/mips/kernel/irq-msc01.c (limited to 'arch/mips/kernel/irq-msc01.c') diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c new file mode 100644 index 00000000000..43c00ac0b88 --- /dev/null +++ b/arch/mips/kernel/irq-msc01.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2004 MIPS Inc + * Author: chris@mips.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static unsigned long _icctrl_msc; +#define MSC01_IC_REG_BASE _icctrl_msc + +#define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) +#define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) + +static unsigned int irq_base; + +/* mask off an interrupt */ +static inline void mask_msc_irq(unsigned int irq) +{ + if (irq < (irq_base + 32)) + MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); + else + MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); +} + +/* unmask an interrupt */ +static inline void unmask_msc_irq(unsigned int irq) +{ + if (irq < (irq_base + 32)) + MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); + else + MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); +} + +/* + * Enables the IRQ on SOC-it + */ +static void enable_msc_irq(unsigned int irq) +{ + unmask_msc_irq(irq); +} + +/* + * Initialize the IRQ on SOC-it + */ +static unsigned int startup_msc_irq(unsigned int irq) +{ + unmask_msc_irq(irq); + return 0; +} + +/* + * Disables the IRQ on SOC-it + */ +static void disable_msc_irq(unsigned int irq) +{ + mask_msc_irq(irq); +} + +/* + * Masks and ACKs an IRQ + */ +static void level_mask_and_ack_msc_irq(unsigned int irq) +{ + mask_msc_irq(irq); + if (!cpu_has_ei) + MSCIC_WRITE(MSC01_IC_EOI, 0); +} + +/* + * Masks and ACKs an IRQ + */ +static void edge_mask_and_ack_msc_irq(unsigned int irq) +{ + mask_msc_irq(irq); + if (!cpu_has_ei) + MSCIC_WRITE(MSC01_IC_EOI, 0); + else { + u32 r; + MSCIC_READ(MSC01_IC_SUP+irq*8, r); + MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); + MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); + } +} + +/* + * End IRQ processing + */ +static void end_msc_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_msc_irq(irq); +} + +/* + * Interrupt handler for interrupts coming from SOC-it. + */ +void ll_msc_irq(struct pt_regs *regs) +{ + unsigned int irq; + + /* read the interrupt vector register */ + MSCIC_READ(MSC01_IC_VEC, irq); + if (irq < 64) + do_IRQ(irq + irq_base, regs); + else { + /* Ignore spurious interrupt */ + } +} + +void +msc_bind_eic_interrupt (unsigned int irq, unsigned int set) +{ + MSCIC_WRITE(MSC01_IC_RAMW, + (irq<= 0; nirq--, imp++) { + int n = imp->im_irq; + + switch (imp->im_type) { + case MSC01_IRQ_EDGE: + irq_desc[base+n].handler = &msc_edgeirq_type; + if (cpu_has_ei) + MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); + else + MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); + break; + case MSC01_IRQ_LEVEL: + irq_desc[base+n].handler = &msc_levelirq_type; + if (cpu_has_ei) + MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); + else + MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); + } + } + + irq_base = base; + + MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ + +} -- cgit v1.2.3