From 237cfee1db66147aef4457f02b56a41e6f84bfd3 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 6 Dec 2007 09:07:55 +0100 Subject: [MIPS] Alchemy: Au1210/Au1250 CPU support This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 2 ++ arch/mips/mm/tlbex.c | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 06074948450..02bd180f0e0 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -980,6 +980,8 @@ static void __init probe_pcache(void) case CPU_AU1100: case CPU_AU1550: case CPU_AU1200: + case CPU_AU1210: + case CPU_AU1250: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index c298344fcb7..d026302e0ec 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -917,6 +917,8 @@ static void __init build_tlb_write_entry(u32 **p, struct label **l, case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: + case CPU_AU1210: + case CPU_AU1250: case CPU_PR4450: i_nop(p); tlbw(p); -- cgit v1.2.3