From 847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Mon, 7 Aug 2006 15:08:01 +0100 Subject: [MIPS] MT: Initialise all writable bits in Cause register to zero. Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an immediate exception when starting the second VPE. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-mt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 93429a4d301..766253c44f3 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -203,7 +203,7 @@ void plat_smp_setup(void) write_vpe_c0_config( read_c0_config()); /* make sure there are no software interrupts pending */ - write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0)); + write_vpe_c0_cause(0); /* Propagate Config7 */ write_vpe_c0_config7(read_c0_config7()); -- cgit v1.2.3