From 00d70419fc8f86db94f56e0191be392c4a57f244 Mon Sep 17 00:00:00 2001 From: "joe@perches.com" Date: Tue, 18 Dec 2007 06:30:12 +1100 Subject: [POWERPC] arch/powerpc/: Spelling fixes Signed-off-by: Joe Perches Signed-off-by: Paul Mackerras --- arch/powerpc/boot/4xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index ebf9e217612..3d0e4f921f1 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -122,7 +122,7 @@ void ibm4xx_denali_fixup_memsize(void) else dpath = 4; /* 32 bits */ - /* get adress pins (rows) */ + /* get address pins (rows) */ val = mfdcr_sdram0(DDR0_42); row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); -- cgit v1.2.3 From 619740384cebe2601a8d307654a22d9ed85f2fcb Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 21 Dec 2007 15:39:26 +1100 Subject: [POWERPC] 4xx: EP405 boards support for arch/powerpc Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD comes from a device-tree property, PCI is working to the point where I can see the video card, USB device, and south bridge. This should work with both EP405 and EP405PC. I've not totally figured out how IRQs are wired on this hardware though, thus at this stage, expect only USB interrupts working, pretty much the same as what arch/ppc did. Also, the flash, nvram, rtc and temp control still have to be wired. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 3d0e4f921f1..852992b146e 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -179,13 +179,16 @@ void ibm40x_dbcr_reset(void) #define EMAC_RESET 0x20000000 void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) { - /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */ + /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't + * do this for us + */ if (emac0) *emac0 = EMAC_RESET; if (emac1) *emac1 = EMAC_RESET; mtdcr(DCRN_MAL0_CFG, MAL_RESET); + while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {}; } /* Read 4xx EBC bus bridge registers to get mappings of the peripheral @@ -298,3 +301,53 @@ void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) dt_fixup_clock("/plb/opb/serial@ef600500", uart0); dt_fixup_clock("/plb/opb/serial@ef600600", uart0); } + +void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +{ + u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); + u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); + u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); + u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; + u32 fwdv, fbdv, cbdv, opdv, epdv, udiv; + + fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); + fbdv = (pllmr & 0x1e000000) >> 25; + cbdv = ((pllmr & 0x00060000) >> 17) + 1; + opdv = ((pllmr & 0x00018000) >> 15) + 1; + epdv = ((pllmr & 0x00001800) >> 13) + 2; + udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; + + m = fwdv * fbdv * cbdv; + + cpu = sysclk * m / fwdv; + plb = cpu / cbdv; + opb = plb / opdv; + ebc = plb / epdv; + + if (cpc0_cr0 & 0x80) { + /* uart0 uses the external clock */ + uart0 = ser_clk; + } else { + uart0 = cpu / udiv; + } + + if (cpc0_cr0 & 0x40) { + /* uart1 uses the external clock */ + uart1 = ser_clk; + } else { + uart1 = cpu / udiv; + } + + /* setup the timebase clock to tick at the cpu frequency */ + cpc0_cr1 = cpc0_cr1 & ~0x00800000; + mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); + tb = cpu; + + dt_fixup_cpu_clocks(cpu, tb, 0); + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@ef600300", uart0); + dt_fixup_clock("/plb/opb/serial@ef600400", uart1); +} + -- cgit v1.2.3 From d23f5099297c0f017ba4fb165dc9879bda11f9ce Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 21 Dec 2007 15:39:31 +1100 Subject: [POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 85 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 15 deletions(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 852992b146e..d16ea10d754 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -22,16 +22,14 @@ #include "dcr.h" /* Read the 4xx SDRAM controller to get size of system memory. */ -void ibm4xx_fixup_memsize(void) +void ibm4xx_sdram_fixup_memsize(void) { int i; unsigned long memsize, bank_config; memsize = 0; for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { - mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]); - bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); - + bank_config = SDRAM0_READ(sdram_bxcr[i]); if (bank_config & SDRAM_CONFIG_BANK_ENABLE) memsize += SDRAM_CONFIG_BANK_SIZE(bank_config); } @@ -39,6 +37,69 @@ void ibm4xx_fixup_memsize(void) dt_fixup_memory(0, memsize); } +/* Read the 440SPe MQ controller to get size of system memory. */ +#define DCRN_MQ0_B0BAS 0x40 +#define DCRN_MQ0_B1BAS 0x41 +#define DCRN_MQ0_B2BAS 0x42 +#define DCRN_MQ0_B3BAS 0x43 + +static u64 ibm440spe_decode_bas(u32 bas) +{ + u64 base = ((u64)(bas & 0xFFE00000u)) << 2; + + /* open coded because I'm paranoid about invalid values */ + switch ((bas >> 4) & 0xFFF) { + case 0: + return 0; + case 0xffc: + return base + 0x000800000ull; + case 0xff8: + return base + 0x001000000ull; + case 0xff0: + return base + 0x002000000ull; + case 0xfe0: + return base + 0x004000000ull; + case 0xfc0: + return base + 0x008000000ull; + case 0xf80: + return base + 0x010000000ull; + case 0xf00: + return base + 0x020000000ull; + case 0xe00: + return base + 0x040000000ull; + case 0xc00: + return base + 0x080000000ull; + case 0x800: + return base + 0x100000000ull; + } + printf("Memory BAS value 0x%08x unsupported !\n", bas); + return 0; +} + +void ibm440spe_fixup_memsize(void) +{ + u64 banktop, memsize = 0; + + /* Ultimately, we should directly construct the memory node + * so we are able to handle holes in the memory address space + */ + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); + if (banktop > memsize) + memsize = banktop; + + dt_fixup_memory(0, memsize); +} + + /* 4xx DDR1/2 Denali memory controller support */ /* DDR0 registers */ #define DDR0_02 2 @@ -77,19 +138,13 @@ void ibm4xx_fixup_memsize(void) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) -static inline u32 mfdcr_sdram0(u32 reg) -{ - mtdcr(DCRN_SDRAM0_CFGADDR, reg); - return mfdcr(DCRN_SDRAM0_CFGDATA); -} - void ibm4xx_denali_fixup_memsize(void) { u32 val, max_cs, max_col, max_row; u32 cs, col, row, bank, dpath; unsigned long memsize; - val = mfdcr_sdram0(DDR0_02); + val = SDRAM0_READ(DDR0_02); if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) fatal("DDR controller is not initialized\n"); @@ -99,7 +154,7 @@ void ibm4xx_denali_fixup_memsize(void) max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); /* get CS value */ - val = mfdcr_sdram0(DDR0_10); + val = SDRAM0_READ(DDR0_10); val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); cs = 0; @@ -115,7 +170,7 @@ void ibm4xx_denali_fixup_memsize(void) fatal("DDR wrong CS configuration\n"); /* get data path bytes */ - val = mfdcr_sdram0(DDR0_14); + val = SDRAM0_READ(DDR0_14); if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) dpath = 8; /* 64 bits */ @@ -123,7 +178,7 @@ void ibm4xx_denali_fixup_memsize(void) dpath = 4; /* 32 bits */ /* get address pins (rows) */ - val = mfdcr_sdram0(DDR0_42); + val = SDRAM0_READ(DDR0_42); row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); if (row > max_row) @@ -131,7 +186,7 @@ void ibm4xx_denali_fixup_memsize(void) row = max_row - row; /* get collomn size and banks */ - val = mfdcr_sdram0(DDR0_43); + val = SDRAM0_READ(DDR0_43); col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT); if (col > max_col) -- cgit v1.2.3 From 190de005384204ba4dc339c3d05f8d40f6b16643 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 21 Dec 2007 15:39:33 +1100 Subject: [POWERPC] 4xx: Rework clock probing in boot wrapper This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 272 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 204 insertions(+), 68 deletions(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index d16ea10d754..1a83efe274c 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -275,89 +275,225 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc) setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); } -#define SPRN_CCR1 0x378 -void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +/* Calculate 440GP clocks */ +void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) { - u32 cpu, plb, opb, ebc, tb, uart0, m, vco; - u32 reg; - u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x000F0000) >> 16; - fwdva = tmp ? tmp : 16; - tmp = (reg & 0x00000700) >> 8; - fwdvb = tmp ? tmp : 8; - tmp = (reg & 0x1F000000) >> 24; - fbdv = tmp ? tmp : 32; - lfbdv = (reg & 0x0000007F); - - mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - opbdv0 = tmp ? tmp : 4; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x07000000) >> 24; - perdv0 = tmp ? tmp : 8; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x07000000) >> 24; - prbdv0 = tmp ? tmp : 8; - - mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - spcid0 = tmp ? tmp : 4; - - /* Calculate M */ - mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - if (tmp == 0) { /* PLL output */ - tmp = (reg & 0x20000000) >> 29; - if (!tmp) /* PLLOUTA */ - m = fbdv * lfbdv * fwdva; + u32 sys0 = mfdcr(DCRN_CPC0_SYS0); + u32 cr0 = mfdcr(DCRN_CPC0_CR0); + u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; + u32 opdv = CPC0_SYS0_OPDV(sys0); + u32 epdv = CPC0_SYS0_EPDV(sys0); + + if (sys0 & CPC0_SYS0_BYPASS) { + /* Bypass system PLL */ + cpu = plb = sys_clk; + } else { + if (sys0 & CPC0_SYS0_EXTSL) + /* PerClk */ + m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv; else - m = fbdv * lfbdv * fwdvb; + /* CPU clock */ + m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0); + cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0); + plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0); } - else if (tmp == 1) /* CPU output */ - m = fbdv * fwdva; + + opb = plb / opdv; + ebc = opb / epdv; + + /* FIXME: Check if this is for all 440GP, or just Ebony */ + if ((mfpvr() & 0xf0000fff) == 0x40000440) + /* Rev. B 440GP, use external system clock */ + tb = sys_clk; else - m = perdv0 * opbdv0 * fwdvb; + /* Rev. C 440GP, errata force us to use internal clock */ + tb = cpu; - vco = (m * sysclk) + (m >> 1); - cpu = vco / fwdva; - plb = vco / fwdvb / prbdv0; - opb = plb / opbdv0; - ebc = plb / perdv0; + if (cr0 & CPC0_CR0_U0EC) + /* External UART clock */ + uart0 = ser_clk; + else + /* Internal UART clock */ + uart0 = plb / CPC0_CR0_UDIV(cr0); + + if (cr0 & CPC0_CR0_U1EC) + /* External UART clock */ + uart1 = ser_clk; + else + /* Internal UART clock */ + uart1 = plb / CPC0_CR0_UDIV(cr0); + + printf("PPC440GP: SysClk = %dMHz (%x)\n\r", + (sys_clk + 500000) / 1000000, sys_clk); + + dt_fixup_cpu_clocks(cpu, tb, 0); + + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/opb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@40000200", uart0); + dt_fixup_clock("/plb/opb/serial@40000300", uart1); +} + +#define SPRN_CCR1 0x378 + +static inline u32 __fix_zero(u32 v, u32 def) +{ + return v ? v : def; +} + +static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk, + unsigned int tmr_clk, + int per_clk_from_opb) +{ + /* PLL config */ + u32 pllc = CPR0_READ(DCRN_CPR0_PLLC); + u32 plld = CPR0_READ(DCRN_CPR0_PLLD); + + /* Dividers */ + u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); + u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); + u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); + u32 lfbdv = __fix_zero(plld & 0x3f, 64); + u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8); + u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8); + u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4); + u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4); + + /* Input clocks for primary dividers */ + u32 clk_a, clk_b; + + /* Resulting clocks */ + u32 cpu, plb, opb, ebc, vco; + + /* Timebase */ + u32 ccr1, tb = tmr_clk; + + if (pllc & 0x40000000) { + u32 m; + + /* Feedback path */ + switch ((pllc >> 24) & 7) { + case 0: + /* PLLOUTx */ + m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; + break; + case 1: + /* CPU */ + m = fwdva * pradv0; + break; + case 5: + /* PERClk */ + m = fwdvb * prbdv0 * opbdv0 * perdv0; + break; + default: + printf("WARNING ! Invalid PLL feedback source !\n"); + goto bypass; + } + m *= fbdv; + vco = sys_clk * m; + clk_a = vco / fwdva; + clk_b = vco / fwdvb; + } else { +bypass: + /* Bypass system PLL */ + vco = 0; + clk_a = clk_b = sys_clk; + } - /* FIXME */ - uart0 = ser_clk; + cpu = clk_a / pradv0; + plb = clk_b / prbdv0; + opb = plb / opbdv0; + ebc = (per_clk_from_opb ? opb : plb) / perdv0; /* Figure out timebase. Either CPU or default TmrClk */ - asm volatile ( - "mfspr %0,%1\n" - : - "=&r"(reg) : "i"(SPRN_CCR1)); - if (reg & 0x0080) - tb = 25000000; /* TmrClk is 25MHz */ - else + ccr1 = mfspr(SPRN_CCR1); + + /* If passed a 0 tmr_clk, force CPU clock */ + if (tb == 0) { + ccr1 &= ~0x80u; + mtspr(SPRN_CCR1, ccr1); + } + if ((ccr1 & 0x0080) == 0) tb = cpu; dt_fixup_cpu_clocks(cpu, tb, 0); dt_fixup_clock("/plb", plb); dt_fixup_clock("/plb/opb", opb); dt_fixup_clock("/plb/opb/ebc", ebc); - dt_fixup_clock("/plb/opb/serial@ef600300", uart0); - dt_fixup_clock("/plb/opb/serial@ef600400", uart0); - dt_fixup_clock("/plb/opb/serial@ef600500", uart0); - dt_fixup_clock("/plb/opb/serial@ef600600", uart0); + + return plb; +} + +static void eplike_fixup_uart_clk(int index, const char *path, + unsigned int ser_clk, + unsigned int plb_clk) +{ + unsigned int sdr; + unsigned int clock; + + switch (index) { + case 0: + sdr = SDR0_READ(DCRN_SDR0_UART0); + break; + case 1: + sdr = SDR0_READ(DCRN_SDR0_UART1); + break; + case 2: + sdr = SDR0_READ(DCRN_SDR0_UART2); + break; + case 3: + sdr = SDR0_READ(DCRN_SDR0_UART3); + break; + default: + return; + } + + if (sdr & 0x00800000u) + clock = ser_clk; + else + clock = plb_clk / __fix_zero(sdr & 0xff, 256); + + dt_fixup_clock(path, clock); +} + +void ibm440ep_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk); + eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk); + eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk); +} + +void ibm440gx_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk); +} + +void ibm440spe_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk); + eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk); } -void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) { u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); @@ -374,7 +510,7 @@ void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) m = fwdv * fbdv * cbdv; - cpu = sysclk * m / fwdv; + cpu = sys_clk * m / fwdv; plb = cpu / cbdv; opb = plb / opdv; ebc = plb / epdv; -- cgit v1.2.3 From 67196d7275fcbc62c41c34400855d3d3c95d8d1d Mon Sep 17 00:00:00 2001 From: Josh Boyer Date: Mon, 24 Dec 2007 19:46:06 -0600 Subject: [POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapper Remove some unneeded braces and make a busy loop more obvious. Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 1a83efe274c..33f25b67134 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -243,7 +243,8 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) *emac1 = EMAC_RESET; mtdcr(DCRN_MAL0_CFG, MAL_RESET); - while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {}; + while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) + ; /* loop until reset takes effect */ } /* Read 4xx EBC bus bridge registers to get mappings of the peripheral @@ -515,19 +516,17 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) opb = plb / opdv; ebc = plb / epdv; - if (cpc0_cr0 & 0x80) { + if (cpc0_cr0 & 0x80) /* uart0 uses the external clock */ uart0 = ser_clk; - } else { + else uart0 = cpu / udiv; - } - if (cpc0_cr0 & 0x40) { + if (cpc0_cr0 & 0x40) /* uart1 uses the external clock */ uart1 = ser_clk; - } else { + else uart1 = cpu / udiv; - } /* setup the timebase clock to tick at the cpu frequency */ cpc0_cr1 = cpc0_cr1 & ~0x00800000; -- cgit v1.2.3 From 2af59f7d5c3e342db4bdd28c59090aee05577aef Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 7 Dec 2007 09:23:05 +1100 Subject: [POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper This patch adds support for 405GPr processors with optional new mode strapping. ibm405gp_fixup_clocks() can now be used for 405GP and 405GPr CPUs. This is in preparation of porting the cpci405 platform support from arch/ppc to arch/powerpc. This patch also adds ibm405ep_fixup_clocks() to support 405EP CPUs from the boot wrapper. Signed-off-by: Matthias Fuchs Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 81 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 7 deletions(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 33f25b67134..61a4045324c 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -499,20 +499,45 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); + u32 psr = mfdcr(DCRN_405_CPC0_PSR); u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; - u32 fwdv, fbdv, cbdv, opdv, epdv, udiv; + u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv; fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); fbdv = (pllmr & 0x1e000000) >> 25; - cbdv = ((pllmr & 0x00060000) >> 17) + 1; - opdv = ((pllmr & 0x00018000) >> 15) + 1; - epdv = ((pllmr & 0x00001800) >> 13) + 2; + if (fbdv == 0) + fbdv = 16; + cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */ + opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */ + ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */ + epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */ udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; - m = fwdv * fbdv * cbdv; + /* check for 405GPr */ + if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) { + fwdvb = 8 - (pllmr & 0x00000007); + if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */ + if (psr & 0x00000020) /* New mode enable */ + m = fwdvb * 2 * ppdv; + else + m = fwdvb * cbdv * ppdv; + else if (psr & 0x00000020) /* New mode enable */ + if (psr & 0x00000800) /* PerClk synch mode */ + m = fwdvb * 2 * epdv; + else + m = fbdv * fwdv; + else if (epdv == fbdv) + m = fbdv * cbdv * epdv; + else + m = fbdv * fwdvb * cbdv; - cpu = sys_clk * m / fwdv; - plb = cpu / cbdv; + cpu = sys_clk * m / fwdv; + plb = sys_clk * m / (fwdvb * cbdv); + } else { + m = fwdv * fbdv * cbdv; + cpu = sys_clk * m / fwdv; + plb = cpu / cbdv; + } opb = plb / opdv; ebc = plb / epdv; @@ -541,3 +566,45 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) dt_fixup_clock("/plb/opb/serial@ef600400", uart1); } + +void ibm405ep_fixup_clocks(unsigned int sys_clk) +{ + u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0); + u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1); + u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR); + u32 cpu, plb, opb, ebc, uart0, uart1; + u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv; + u32 pllmr0_ccdv, tb, m; + + fwdva = 8 - ((pllmr1 & 0x00070000) >> 16); + fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12); + fbdv = (pllmr1 & 0x00f00000) >> 20; + if (fbdv == 0) + fbdv = 16; + + cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */ + epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */ + opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */ + + m = fbdv * fwdvb; + + pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1; + if (pllmr1 & 0x80000000) + cpu = sys_clk * m / (fwdva * pllmr0_ccdv); + else + cpu = sys_clk / pllmr0_ccdv; + + plb = cpu / cbdv; + opb = plb / opdv; + ebc = plb / epdv; + tb = cpu; + uart0 = cpu / (cpc0_ucr & 0x0000007f); + uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8); + + dt_fixup_cpu_clocks(cpu, tb, 0); + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@ef600300", uart0); + dt_fixup_clock("/plb/opb/serial@ef600400", uart1); +} -- cgit v1.2.3 From e08029675181a16d435431ad51255aa730fd6772 Mon Sep 17 00:00:00 2001 From: Roel Kluin <12o3l@tiscali.nl> Date: Thu, 24 Jan 2008 09:37:33 +1100 Subject: [POWERPC] 4xx: logical/bitand typo in powerpc/boot/4xx.c logical/bitand typo Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Josh Boyer --- arch/powerpc/boot/4xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot/4xx.c') diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 61a4045324c..758edf1c581 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -159,7 +159,7 @@ void ibm4xx_denali_fixup_memsize(void) val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); cs = 0; while (val) { - if (val && 0x1) + if (val & 0x1) cs++; val = val >> 1; } -- cgit v1.2.3