From d58577d8f36f66dbb5dec30fc01dfddda0cfd1fa Mon Sep 17 00:00:00 2001 From: John Linn Date: Wed, 2 Jul 2008 15:11:28 -0700 Subject: powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440 The following changes add processing to initialize the Xilinx 16550 UART in the boot wrapper for Virtex targets without firmware. Normally the boot wrapper assumes that the serial port has already been initialized by firmware. The wrapper was also modified to add the 440 build. Signed-off-by: John Linn Signed-off-by: Grant Likely --- arch/powerpc/boot/wrapper | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/boot/wrapper') diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index df2358e9f1c..592a6ea474f 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -207,7 +207,11 @@ adder875-redboot) binary=y ;; simpleboot-virtex405-*) - platformo="$object/virtex405-head.o $object/simpleboot.o" + platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o" + binary=y + ;; +simpleboot-virtex440-*) + platformo="$object/simpleboot.o $object/virtex.o" binary=y ;; asp834x-redboot) -- cgit v1.2.3