From 9065762edf5ac90e312af1f81e03dc2c964d5a86 Mon Sep 17 00:00:00 2001 From: Geoff Levand Date: Sat, 16 Jun 2007 08:06:51 +1000 Subject: [POWERPC] PS3: Device tree source The PS3 device tree source. Signed-off-by: Geoff Levand Acked-by: Segher Boessenkool Signed-off-by: Paul Mackerras --- arch/powerpc/boot/dts/ps3.dts | 68 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 arch/powerpc/boot/dts/ps3.dts (limited to 'arch/powerpc/boot') diff --git a/arch/powerpc/boot/dts/ps3.dts b/arch/powerpc/boot/dts/ps3.dts new file mode 100644 index 00000000000..379ded282d5 --- /dev/null +++ b/arch/powerpc/boot/dts/ps3.dts @@ -0,0 +1,68 @@ +/* + * PS3 Game Console device tree. + * + * Copyright (C) 2007 Sony Computer Entertainment Inc. + * Copyright 2007 Sony Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/ { + model = "SonyPS3"; + compatible = "sony,ps3"; + #size-cells = <2>; + #address-cells = <2>; + + chosen { + }; + + /* + * We'll get the size of the bootmem block from lv1 after startup, + * so we'll put a null entry here. + */ + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + /* + * The boot cpu is always zero for PS3. + * + * dtc expects a clock-frequency and timebase-frequency entries, so + * we'll put a null entries here. These will be initialized after + * startup with data from lv1. + * + * Seems the only way currently to indicate a processor has multiple + * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one + * here so we can bring up both of ours. See smp_setup_cpu_maps(). + */ + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + ibm,ppc-interrupt-server#s = <0 1>; + clock-frequency = <0>; + timebase-frequency = <0>; + i-cache-size = <8000>; + d-cache-size = <8000>; + i-cache-line-size = <80>; + d-cache-line-size = <80>; + }; + }; +}; -- cgit v1.2.3