From 4481e8eea761857367162b0957277d5524fbea63 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 6 Jun 2005 13:35:57 -0700 Subject: [PATCH] ppc32: Fix incorrect CPU_FTR fixup usage for unified caches Runtime feature support for unified caches was testing a userland feature flag (PPC_FEATURE_UNIFIED_CACHE) instead of a cpu feature flag (CPU_FTR_SPLIT_ID_CACHE). Luckily the current defined bit mask for cpu features and userland features do not overlap so this only causes an issue on machines with a unified cache, which is extremely rare on PPC today. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/misc.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index e4f1615ec13..7329ef177a1 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -619,7 +619,7 @@ _GLOBAL(flush_instruction_cache) _GLOBAL(flush_icache_range) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) li r5,L1_CACHE_LINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 @@ -736,7 +736,7 @@ _GLOBAL(flush_dcache_all) _GLOBAL(__flush_dcache_icache) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) rlwinm r3,r3,0,0,19 /* Get page base address */ li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ mtctr r4 @@ -764,7 +764,7 @@ END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) _GLOBAL(__flush_dcache_icache_phys) BEGIN_FTR_SECTION blr /* for 601, do nothing */ -END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) +END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) mfmsr r10 rlwinm r0,r10,0,28,26 /* clear DR */ mtmsr r0 -- cgit v1.2.3 From ad95d6098dd1e94a09d2a1fdf39fd8281fcd8958 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Tue, 7 Jun 2005 13:22:09 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 8aa5e8c6900..d44b7dc5390 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -838,6 +838,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From beb9e1c3f32a0f878765c7c1142f91083739c5bd Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Wed, 8 Jun 2005 15:48:42 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index d44b7dc5390..17abf6cd0d9 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -849,6 +849,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From 7fbdf1a23be1837b8bc5bcec096015ca99e00aa7 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Thu, 9 Jun 2005 12:36:29 -0700 Subject: [PATCH] ppc32: add 405EP cpu_spec entry Add a definition for PPC 405EP which was lost somehow during 2.4 -> 2.6 transition. Recent change to arch/ppc/kernel/misc.S ("Fix incorrect CPU_FTR fixup usage for unified caches") triggered this bug and 405EP boards don't boot anymore. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 17abf6cd0d9..ce2618ac8ac 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -860,6 +860,17 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 405EP */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x51210000, + .cpu_name = "405EP", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | + PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3 From 90abb7b5f3bd9271a455cd640a70c285b4fd0c89 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 10 Jun 2005 09:37:21 -0700 Subject: ppc: remove two extraneous descriptors for the 405EP CPU The patch to add them keeps on getting applied, over and over again ;) Hopefully no more. --- arch/ppc/kernel/cputable.c | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index ce2618ac8ac..d44b7dc5390 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -849,28 +849,6 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, - { /* 405EP */ - .pvr_mask = 0xffff0000, - .pvr_value = 0x51210000, - .cpu_name = "405EP", - .cpu_features = CPU_FTR_SPLIT_ID_CACHE | - CPU_FTR_USE_TB, - .cpu_user_features = PPC_FEATURE_32 | - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, - .icache_bsize = 32, - .dcache_bsize = 32, - }, - { /* 405EP */ - .pvr_mask = 0xffff0000, - .pvr_value = 0x51210000, - .cpu_name = "405EP", - .cpu_features = CPU_FTR_SPLIT_ID_CACHE | - CPU_FTR_USE_TB, - .cpu_user_features = PPC_FEATURE_32 | - PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, - .icache_bsize = 32, - .dcache_bsize = 32, - }, #endif /* CONFIG_40x */ #ifdef CONFIG_44x -- cgit v1.2.3