From 3155f7f23f7865e64f7eb14e226a2dff8197e51f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 25 Jan 2008 15:41:00 -0600 Subject: [PPC] Remove 83xx from arch/ppc 83xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala --- arch/ppc/syslib/Makefile | 5 - arch/ppc/syslib/ipic.c | 646 -------------------------------------- arch/ppc/syslib/ipic.h | 47 --- arch/ppc/syslib/mpc83xx_devices.c | 251 --------------- arch/ppc/syslib/mpc83xx_sys.c | 122 ------- arch/ppc/syslib/ppc83xx_pci.h | 151 --------- arch/ppc/syslib/ppc83xx_setup.c | 410 ------------------------ arch/ppc/syslib/ppc83xx_setup.h | 55 ---- 8 files changed, 1687 deletions(-) delete mode 100644 arch/ppc/syslib/ipic.c delete mode 100644 arch/ppc/syslib/ipic.h delete mode 100644 arch/ppc/syslib/mpc83xx_devices.c delete mode 100644 arch/ppc/syslib/mpc83xx_sys.c delete mode 100644 arch/ppc/syslib/ppc83xx_pci.h delete mode 100644 arch/ppc/syslib/ppc83xx_setup.c delete mode 100644 arch/ppc/syslib/ppc83xx_setup.h (limited to 'arch/ppc/syslib') diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 5e16228f764..4d158f3bd47 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -93,11 +93,6 @@ obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \ ifeq ($(CONFIG_85xx),y) obj-$(CONFIG_PCI) += pci_auto.o endif -obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \ - mpc83xx_sys.o mpc83xx_devices.o ipic.o -ifeq ($(CONFIG_83xx),y) -obj-$(CONFIG_PCI) += pci_auto.o -endif obj-$(CONFIG_MPC8548_CDS) += todc_time.o obj-$(CONFIG_MPC8555_CDS) += todc_time.o obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c deleted file mode 100644 index 9192777d0f7..00000000000 --- a/arch/ppc/syslib/ipic.c +++ /dev/null @@ -1,646 +0,0 @@ -/* - * arch/ppc/syslib/ipic.c - * - * IPIC routines implementations. - * - * Copyright 2005 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ipic.h" - -static struct ipic p_ipic; -static struct ipic * primary_ipic; - -static struct ipic_info ipic_info[] = { - [9] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 24, - .prio_mask = 0, - }, - [10] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 25, - .prio_mask = 1, - }, - [11] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 26, - .prio_mask = 2, - }, - [14] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 29, - .prio_mask = 5, - }, - [15] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 30, - .prio_mask = 6, - }, - [16] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_D, - .force = IPIC_SIFCR_H, - .bit = 31, - .prio_mask = 7, - }, - [17] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 1, - .prio_mask = 5, - }, - [18] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 2, - .prio_mask = 6, - }, - [19] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 3, - .prio_mask = 7, - }, - [20] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 4, - .prio_mask = 4, - }, - [21] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 5, - .prio_mask = 5, - }, - [22] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 6, - .prio_mask = 6, - }, - [23] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_B, - .force = IPIC_SEFCR, - .bit = 7, - .prio_mask = 7, - }, - [32] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 0, - .prio_mask = 0, - }, - [33] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 1, - .prio_mask = 1, - }, - [34] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 2, - .prio_mask = 2, - }, - [35] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 3, - .prio_mask = 3, - }, - [36] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 4, - .prio_mask = 4, - }, - [37] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 5, - .prio_mask = 5, - }, - [38] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 6, - .prio_mask = 6, - }, - [39] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_H, - .prio = IPIC_SIPRR_A, - .force = IPIC_SIFCR_H, - .bit = 7, - .prio_mask = 7, - }, - [48] = { - .pend = IPIC_SEPNR, - .mask = IPIC_SEMSR, - .prio = IPIC_SMPRR_A, - .force = IPIC_SEFCR, - .bit = 0, - .prio_mask = 4, - }, - [64] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 0, - .prio_mask = 0, - }, - [65] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 1, - .prio_mask = 1, - }, - [66] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 2, - .prio_mask = 2, - }, - [67] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_A, - .force = IPIC_SIFCR_L, - .bit = 3, - .prio_mask = 3, - }, - [68] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 4, - .prio_mask = 0, - }, - [69] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 5, - .prio_mask = 1, - }, - [70] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 6, - .prio_mask = 2, - }, - [71] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = IPIC_SMPRR_B, - .force = IPIC_SIFCR_L, - .bit = 7, - .prio_mask = 3, - }, - [72] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 8, - }, - [73] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 9, - }, - [74] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 10, - }, - [75] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 11, - }, - [76] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 12, - }, - [77] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 13, - }, - [78] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 14, - }, - [79] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 15, - }, - [80] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 16, - }, - [84] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 20, - }, - [85] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 21, - }, - [90] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 26, - }, - [91] = { - .pend = IPIC_SIPNR_H, - .mask = IPIC_SIMSR_L, - .prio = 0, - .force = IPIC_SIFCR_L, - .bit = 27, - }, -}; - -static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) -{ - return in_be32(base + (reg >> 2)); -} - -static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) -{ - out_be32(base + (reg >> 2), value); -} - -static inline struct ipic * ipic_from_irq(unsigned int irq) -{ - return primary_ipic; -} - -static void ipic_enable_irq(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, ipic_info[src].mask); - temp |= (1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].mask, temp); -} - -static void ipic_disable_irq(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, ipic_info[src].mask); - temp &= ~(1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].mask, temp); -} - -static void ipic_disable_irq_and_ack(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - ipic_disable_irq(irq); - - temp = ipic_read(ipic->regs, ipic_info[src].pend); - temp |= (1 << (31 - ipic_info[src].bit)); - ipic_write(ipic->regs, ipic_info[src].pend, temp); -} - -static void ipic_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - ipic_enable_irq(irq); -} - -struct hw_interrupt_type ipic = { - .typename = " IPIC ", - .enable = ipic_enable_irq, - .disable = ipic_disable_irq, - .ack = ipic_disable_irq_and_ack, - .end = ipic_end_irq, -}; - -void __init ipic_init(phys_addr_t phys_addr, - unsigned int flags, - unsigned int irq_offset, - unsigned char *senses, - unsigned int senses_count) -{ - u32 i, temp = 0; - - primary_ipic = &p_ipic; - primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE); - - primary_ipic->irq_offset = irq_offset; - - ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); - - /* default priority scheme is grouped. If spread mode is required - * configure SICFR accordingly */ - if (flags & IPIC_SPREADMODE_GRP_A) - temp |= SICFR_IPSA; - if (flags & IPIC_SPREADMODE_GRP_D) - temp |= SICFR_IPSD; - if (flags & IPIC_SPREADMODE_MIX_A) - temp |= SICFR_MPSA; - if (flags & IPIC_SPREADMODE_MIX_B) - temp |= SICFR_MPSB; - - ipic_write(primary_ipic->regs, IPIC_SICNR, temp); - - /* handle MCP route */ - temp = 0; - if (flags & IPIC_DISABLE_MCP_OUT) - temp = SERCR_MCPR; - ipic_write(primary_ipic->regs, IPIC_SERCR, temp); - - /* handle routing of IRQ0 to MCP */ - temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); - - if (flags & IPIC_IRQ0_MCP) - temp |= SEMSR_SIRQ0; - else - temp &= ~SEMSR_SIRQ0; - - ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); - - for (i = 0 ; i < NR_IPIC_INTS ; i++) { - irq_desc[i+irq_offset].chip = &ipic; - irq_desc[i+irq_offset].status = IRQ_LEVEL; - } - - temp = 0; - for (i = 0 ; i < senses_count ; i++) { - if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) { - temp |= 1 << (15 - i); - if (i != 0) - irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0; - else - irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0; - } - } - ipic_write(primary_ipic->regs, IPIC_SECNR, temp); - - printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS, - senses_count, primary_ipic->regs); -} - -int ipic_set_priority(unsigned int irq, unsigned int priority) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - if (priority > 7) - return -EINVAL; - if (src > 127) - return -EINVAL; - if (ipic_info[src].prio == 0) - return -EINVAL; - - temp = ipic_read(ipic->regs, ipic_info[src].prio); - - if (priority < 4) { - temp &= ~(0x7 << (20 + (3 - priority) * 3)); - temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3); - } else { - temp &= ~(0x7 << (4 + (7 - priority) * 3)); - temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3); - } - - ipic_write(ipic->regs, ipic_info[src].prio, temp); - - return 0; -} - -void ipic_set_highest_priority(unsigned int irq) -{ - struct ipic *ipic = ipic_from_irq(irq); - unsigned int src = irq - ipic->irq_offset; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SICFR); - - /* clear and set HPI */ - temp &= 0x7f000000; - temp |= (src & 0x7f) << 24; - - ipic_write(ipic->regs, IPIC_SICFR, temp); -} - -void ipic_set_default_priority(void) -{ - ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); - ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); - ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); - ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); - ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4); - ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5); - ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6); - ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7); - - ipic_set_priority(MPC83xx_IRQ_UART1, 0); - ipic_set_priority(MPC83xx_IRQ_UART2, 1); - ipic_set_priority(MPC83xx_IRQ_SEC2, 2); - ipic_set_priority(MPC83xx_IRQ_IIC1, 5); - ipic_set_priority(MPC83xx_IRQ_IIC2, 6); - ipic_set_priority(MPC83xx_IRQ_SPI, 7); - ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0); - ipic_set_priority(MPC83xx_IRQ_PIT, 1); - ipic_set_priority(MPC83xx_IRQ_PCI1, 2); - ipic_set_priority(MPC83xx_IRQ_PCI2, 3); - ipic_set_priority(MPC83xx_IRQ_EXT0, 4); - ipic_set_priority(MPC83xx_IRQ_EXT1, 5); - ipic_set_priority(MPC83xx_IRQ_EXT2, 6); - ipic_set_priority(MPC83xx_IRQ_EXT3, 7); - ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0); - ipic_set_priority(MPC83xx_IRQ_MU, 1); - ipic_set_priority(MPC83xx_IRQ_SBA, 2); - ipic_set_priority(MPC83xx_IRQ_DMA, 3); - ipic_set_priority(MPC83xx_IRQ_EXT4, 4); - ipic_set_priority(MPC83xx_IRQ_EXT5, 5); - ipic_set_priority(MPC83xx_IRQ_EXT6, 6); - ipic_set_priority(MPC83xx_IRQ_EXT7, 7); -} - -void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) -{ - struct ipic *ipic = primary_ipic; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SERMR); - temp |= (1 << (31 - mcp_irq)); - ipic_write(ipic->regs, IPIC_SERMR, temp); -} - -void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq) -{ - struct ipic *ipic = primary_ipic; - u32 temp; - - temp = ipic_read(ipic->regs, IPIC_SERMR); - temp &= (1 << (31 - mcp_irq)); - ipic_write(ipic->regs, IPIC_SERMR, temp); -} - -u32 ipic_get_mcp_status(void) -{ - return ipic_read(primary_ipic->regs, IPIC_SERMR); -} - -void ipic_clear_mcp_status(u32 mask) -{ - ipic_write(primary_ipic->regs, IPIC_SERMR, mask); -} - -/* Return an interrupt vector or -1 if no interrupt is pending. */ -int ipic_get_irq(void) -{ - int irq; - - irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; - - if (irq == 0) /* 0 --> no irq is pending */ - irq = -1; - - return irq; -} - -static struct sysdev_class ipic_sysclass = { - set_kset_name("ipic"), -}; - -static struct sys_device device_ipic = { - .id = 0, - .cls = &ipic_sysclass, -}; - -static int __init init_ipic_sysfs(void) -{ - int rc; - - if (!primary_ipic->regs) - return -ENODEV; - printk(KERN_DEBUG "Registering ipic with sysfs...\n"); - - rc = sysdev_class_register(&ipic_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering ipic sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&device_ipic); - if (rc) { - printk(KERN_ERR "Failed registering ipic sys device\n"); - return -ENODEV; - } - return 0; -} - -subsys_initcall(init_ipic_sysfs); diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h deleted file mode 100644 index a60c9d18bb7..00000000000 --- a/arch/ppc/syslib/ipic.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * IPIC private definitions and structure. - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef __IPIC_H__ -#define __IPIC_H__ - -#include - -#define MPC83xx_IPIC_SIZE (0x00100) - -/* System Global Interrupt Configuration Register */ -#define SICFR_IPSA 0x00010000 -#define SICFR_IPSD 0x00080000 -#define SICFR_MPSA 0x00200000 -#define SICFR_MPSB 0x00400000 - -/* System External Interrupt Mask Register */ -#define SEMSR_SIRQ0 0x00008000 - -/* System Error Control Register */ -#define SERCR_MCPR 0x00000001 - -struct ipic { - volatile u32 __iomem *regs; - unsigned int irq_offset; -}; - -struct ipic_info { - u8 pend; /* pending register offset from base */ - u8 mask; /* mask register offset from base */ - u8 prio; /* priority register offset from base */ - u8 force; /* force register offset from base */ - u8 bit; /* register bit position (as per doc) - bit mask = 1 << (31 - bit) */ - u8 prio_mask; /* priority mask value */ -}; - -#endif /* __IPIC_H__ */ diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c deleted file mode 100644 index 5c4932ca8e9..00000000000 --- a/arch/ppc/syslib/mpc83xx_devices.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * MPC83xx Device descriptions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* We use offsets for IORESOURCE_MEM since we do not know at compile time - * what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup - */ - -struct gianfar_mdio_data mpc83xx_mdio_pdata = { -}; - -static struct gianfar_platform_data mpc83xx_tsec1_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct gianfar_platform_data mpc83xx_tsec2_pdata = { - .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | - FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | - FSL_GIANFAR_DEV_HAS_MULTI_INTR, -}; - -static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = { - .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, -}; - -static struct plat_serial8250_port serial_platform_data[] = { - [0] = { - .mapbase = 0x4500, - .irq = MPC83xx_IRQ_UART1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - [1] = { - .mapbase = 0x4600, - .irq = MPC83xx_IRQ_UART2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -struct platform_device ppc_sys_platform_devices[] = { - [MPC83xx_TSEC1] = { - .name = "fsl-gianfar", - .id = 1, - .dev.platform_data = &mpc83xx_tsec1_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = 0x24000, - .end = 0x24fff, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC83xx_IRQ_TSEC1_TX, - .end = MPC83xx_IRQ_TSEC1_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC83xx_IRQ_TSEC1_RX, - .end = MPC83xx_IRQ_TSEC1_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC83xx_IRQ_TSEC1_ERROR, - .end = MPC83xx_IRQ_TSEC1_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_TSEC2] = { - .name = "fsl-gianfar", - .id = 2, - .dev.platform_data = &mpc83xx_tsec2_pdata, - .num_resources = 4, - .resource = (struct resource[]) { - { - .start = 0x25000, - .end = 0x25fff, - .flags = IORESOURCE_MEM, - }, - { - .name = "tx", - .start = MPC83xx_IRQ_TSEC2_TX, - .end = MPC83xx_IRQ_TSEC2_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = MPC83xx_IRQ_TSEC2_RX, - .end = MPC83xx_IRQ_TSEC2_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "error", - .start = MPC83xx_IRQ_TSEC2_ERROR, - .end = MPC83xx_IRQ_TSEC2_ERROR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_IIC1] = { - .name = "fsl-i2c", - .id = 1, - .dev.platform_data = &mpc83xx_fsl_i2c1_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3000, - .end = 0x30ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_IIC1, - .end = MPC83xx_IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_IIC2] = { - .name = "fsl-i2c", - .id = 2, - .dev.platform_data = &mpc83xx_fsl_i2c2_pdata, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x3100, - .end = 0x31ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_IIC2, - .end = MPC83xx_IRQ_IIC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_DUART] = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial_platform_data, - }, - [MPC83xx_SEC2] = { - .name = "fsl-sec2", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x30000, - .end = 0x3ffff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_SEC2, - .end = MPC83xx_IRQ_SEC2, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_USB2_DR] = { - .name = "fsl-ehci", - .id = 1, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x23000, - .end = 0x23fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_USB2_DR, - .end = MPC83xx_IRQ_USB2_DR, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_USB2_MPH] = { - .name = "fsl-ehci", - .id = 2, - .num_resources = 2, - .resource = (struct resource[]) { - { - .start = 0x22000, - .end = 0x22fff, - .flags = IORESOURCE_MEM, - }, - { - .start = MPC83xx_IRQ_USB2_MPH, - .end = MPC83xx_IRQ_USB2_MPH, - .flags = IORESOURCE_IRQ, - }, - }, - }, - [MPC83xx_MDIO] = { - .name = "fsl-gianfar_mdio", - .id = 0, - .dev.platform_data = &mpc83xx_mdio_pdata, - .num_resources = 1, - .resource = (struct resource[]) { - { - .start = 0x24520, - .end = 0x2453f, - .flags = IORESOURCE_MEM, - }, - }, - }, -}; - -static int __init mach_mpc83xx_fixup(struct platform_device *pdev) -{ - ppc_sys_fixup_mem_resource(pdev, immrbar); - return 0; -} - -static int __init mach_mpc83xx_init(void) -{ - if (ppc_md.progress) - ppc_md.progress("mach_mpc83xx_init:enter", 0); - ppc_sys_device_fixup = mach_mpc83xx_fixup; - return 0; -} - -postcore_initcall(mach_mpc83xx_init); diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c deleted file mode 100644 index 0498ae7e01e..00000000000 --- a/arch/ppc/syslib/mpc83xx_sys.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * MPC83xx System descriptions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include - -struct ppc_sys_spec *cur_ppc_sys_spec; -struct ppc_sys_spec ppc_sys_specs[] = { - { - .ppc_sys_name = "8349E", - .mask = 0xFFFF0000, - .value = 0x80500000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8349", - .mask = 0xFFFF0000, - .value = 0x80510000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347E", - .mask = 0xFFFF0000, - .value = 0x80520000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347", - .mask = 0xFFFF0000, - .value = 0x80530000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347E", - .mask = 0xFFFF0000, - .value = 0x80540000, - .num_devices = 9, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8347", - .mask = 0xFFFF0000, - .value = 0x80550000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8343E", - .mask = 0xFFFF0000, - .value = 0x80560000, - .num_devices = 8, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, - MPC83xx_USB2_DR, MPC83xx_MDIO - }, - }, - { - .ppc_sys_name = "8343", - .mask = 0xFFFF0000, - .value = 0x80570000, - .num_devices = 7, - .device_list = (enum ppc_sys_devices[]) - { - MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, - MPC83xx_IIC2, MPC83xx_DUART, - MPC83xx_USB2_DR, MPC83xx_MDIO - }, - }, - { /* default match */ - .ppc_sys_name = "", - .mask = 0x00000000, - .value = 0x00000000, - }, -}; diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h deleted file mode 100644 index ec691640f6b..00000000000 --- a/arch/ppc/syslib/ppc83xx_pci.h +++ /dev/null @@ -1,151 +0,0 @@ -/* Created by Tony Li - * Copyright (c) 2005 freescale semiconductor - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __PPC_SYSLIB_PPC83XX_PCI_H -#define __PPC_SYSLIB_PPC83XX_PCI_H - -typedef struct immr_clk { - u32 spmr; /* system PLL mode Register */ - u32 occr; /* output clock control Register */ - u32 sccr; /* system clock control Register */ - u8 res0[0xF4]; -} immr_clk_t; - -/* - * Sequencer - */ -typedef struct immr_ios { - u32 potar0; - u8 res0[4]; - u32 pobar0; - u8 res1[4]; - u32 pocmr0; - u8 res2[4]; - u32 potar1; - u8 res3[4]; - u32 pobar1; - u8 res4[4]; - u32 pocmr1; - u8 res5[4]; - u32 potar2; - u8 res6[4]; - u32 pobar2; - u8 res7[4]; - u32 pocmr2; - u8 res8[4]; - u32 potar3; - u8 res9[4]; - u32 pobar3; - u8 res10[4]; - u32 pocmr3; - u8 res11[4]; - u32 potar4; - u8 res12[4]; - u32 pobar4; - u8 res13[4]; - u32 pocmr4; - u8 res14[4]; - u32 potar5; - u8 res15[4]; - u32 pobar5; - u8 res16[4]; - u32 pocmr5; - u8 res17[4]; - u8 res18[0x60]; - u32 pmcr; - u8 res19[4]; - u32 dtcr; - u8 res20[4]; -} immr_ios_t; -#define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff - -/* - * PCI Controller Control and Status Registers - */ -typedef struct immr_pcictrl { - u32 esr; - u32 ecdr; - u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} immr_pcictrl_t; -#define PITAR_TA_MASK 0x000fffff -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E - -#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */ diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c deleted file mode 100644 index ea372914dd6..00000000000 --- a/arch/ppc/syslib/ppc83xx_setup.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * MPC83XX common board code - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Added PCI support -- Tony Li - */ - -#include -#include -#include -#include -#include -#include /* for linux/serial_core.h */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#if defined(CONFIG_PCI) -#include -#endif - -phys_addr_t immrbar; - -/* Return the amount of memory */ -unsigned long __init -mpc83xx_find_end_of_memory(void) -{ - bd_t *binfo; - - binfo = (bd_t *) __res; - - return binfo->bi_memsize; -} - -long __init -mpc83xx_time_init(void) -{ -#define SPCR_OFFS 0x00000110 -#define SPCR_TBEN 0x00400000 - - bd_t *binfo = (bd_t *)__res; - u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4); - - *spcr |= SPCR_TBEN; - - iounmap(spcr); - - return 0; -} - -/* The decrementer counts at the system (internal) clock freq divided by 4 */ -void __init -mpc83xx_calibrate_decr(void) -{ - bd_t *binfo = (bd_t *) __res; - unsigned int freq, divisor; - - freq = binfo->bi_busfreq; - divisor = 4; - tb_ticks_per_jiffy = freq / HZ / divisor; - tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); -} - -#ifdef CONFIG_SERIAL_8250 -void __init -mpc83xx_early_serial_map(void) -{ -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - struct uart_port serial_req; -#endif - struct plat_serial8250_port *pdata; - bd_t *binfo = (bd_t *) __res; - pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); - - /* Setup serial port access */ - pdata[0].uartclk = binfo->bi_busfreq; - pdata[0].mapbase += binfo->bi_immr_base; - pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - memset(&serial_req, 0, sizeof (serial_req)); - serial_req.iotype = UPIO_MEM; - serial_req.mapbase = pdata[0].mapbase; - serial_req.membase = pdata[0].membase; - serial_req.regshift = 0; - - gen550_init(0, &serial_req); -#endif - - pdata[1].uartclk = binfo->bi_busfreq; - pdata[1].mapbase += binfo->bi_immr_base; - pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); - -#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) - /* Assume gen550_init() doesn't modify serial_req */ - serial_req.mapbase = pdata[1].mapbase; - serial_req.membase = pdata[1].membase; - - gen550_init(1, &serial_req); -#endif -} -#endif - -void -mpc83xx_restart(char *cmd) -{ - volatile unsigned char __iomem *reg; - unsigned char tmp; - - reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); - - local_irq_disable(); - - /* - * Unlock the BCSR bits so a PRST will update the contents. - * Otherwise the reset asserts but doesn't clear. - */ - tmp = in_8(reg + BCSR_MISC_REG3_OFF); - tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ - out_8(reg + BCSR_MISC_REG3_OFF, tmp); - - /* - * Trigger a reset via a low->high transition of the - * PORESET bit. - */ - tmp = in_8(reg + BCSR_MISC_REG2_OFF); - tmp &= ~BCSR_MISC_REG2_PORESET; - out_8(reg + BCSR_MISC_REG2_OFF, tmp); - - udelay(1); - - tmp |= BCSR_MISC_REG2_PORESET; - out_8(reg + BCSR_MISC_REG2_OFF, tmp); - - for(;;); -} - -void -mpc83xx_power_off(void) -{ - local_irq_disable(); - for(;;); -} - -void -mpc83xx_halt(void) -{ - local_irq_disable(); - for(;;); -} - -#if defined(CONFIG_PCI) -void __init -mpc83xx_setup_pci1(struct pci_controller *hose) -{ - u16 reg16; - volatile immr_pcictrl_t * pci_ctrl; - volatile immr_ios_t * ios; - bd_t *binfo = (bd_t *) __res; - - pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); - ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); - - /* - * Configure PCI Outbound Translation Windows - */ - ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; - ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; - ios->pocmr0 = POCMR_EN | - (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - - MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); - - /* mapped to PCI1 IO space */ - ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; - ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; - ios->pocmr1 = POCMR_EN | POCMR_IO | - (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - - MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl->pitar1 = 0x0; - pci_ctrl->pibar1 = 0x0; - pci_ctrl->piebar1 = 0x0; - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - - /* - * Release PCI RST signal - */ - pci_ctrl->gcr = 0; - udelay(2000); - pci_ctrl->gcr = 1; - udelay(2000); - - reg16 = 0xff; - early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); - early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); - - iounmap(pci_ctrl); - iounmap(ios); -} - -void __init -mpc83xx_setup_pci2(struct pci_controller *hose) -{ - u16 reg16; - volatile immr_pcictrl_t * pci_ctrl; - volatile immr_ios_t * ios; - bd_t *binfo = (bd_t *) __res; - - pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); - ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); - - /* - * Configure PCI Outbound Translation Windows - */ - ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; - ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; - ios->pocmr3 = POCMR_EN | POCMR_DST | - (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - - MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); - - /* mapped to PCI2 IO space */ - ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; - ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; - ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | - (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - - MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl->pitar1 = 0x0; - pci_ctrl->pibar1 = 0x0; - pci_ctrl->piebar1 = 0x0; - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; - - /* - * Release PCI RST signal - */ - pci_ctrl->gcr = 0; - udelay(2000); - pci_ctrl->gcr = 1; - udelay(2000); - - reg16 = 0xff; - early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); - early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); - - iounmap(pci_ctrl); - iounmap(ios); -} - -/* - * PCI buses can be enabled only if SYS board combinates with PIB - * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses - * and 3 PCI slots, so people must configure the routes between them before - * enable PCI bus. This routes are under the control of PCA9555PW device which - * can be accessed via I2C bus 2 and are configured by firmware. Refer to - * Freescale to get more information about firmware configuration. - */ - -extern int mpc83xx_exclude_device(u_char bus, u_char devfn); -extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, - unsigned char pin); -void __init -mpc83xx_setup_hose(void) -{ - u32 val32; - volatile immr_clk_t * clk; - struct pci_controller * hose1; -#ifdef CONFIG_MPC83xx_PCI2 - struct pci_controller * hose2; -#endif - bd_t * binfo = (bd_t *)__res; - - clk = ioremap(binfo->bi_immr_base + 0xA00, - sizeof(immr_clk_t)); - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); - clk->occr = 0xff000000; - udelay(2000); - - iounmap(clk); - - hose1 = pcibios_alloc_controller(); - if(!hose1) - return; - - ppc_md.pci_swizzle = common_swizzle; - ppc_md.pci_map_irq = mpc83xx_map_irq; - - hose1->bus_offset = 0; - hose1->first_busno = 0; - hose1->last_busno = 0xff; - - setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); - hose1->set_cfg_type = 1; - - mpc83xx_setup_pci1(hose1); - - hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; - hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; - hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; - - hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; - hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; - hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; -#ifdef CONFIG_MPC83xx_PCI2 - isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, - MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); -#else - isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, - MPC83xx_PCI1_IO_SIZE); -#endif /* CONFIG_MPC83xx_PCI2 */ - hose1->io_base_virt = (void *)isa_io_base; - /* setup resources */ - pci_init_resource(&hose1->io_resource, - MPC83xx_PCI1_LOWER_IO, - MPC83xx_PCI1_UPPER_IO, - IORESOURCE_IO, "PCI host bridge 1"); - pci_init_resource(&hose1->mem_resources[0], - MPC83xx_PCI1_LOWER_MEM, - MPC83xx_PCI1_UPPER_MEM, - IORESOURCE_MEM, "PCI host bridge 1"); - - ppc_md.pci_exclude_device = mpc83xx_exclude_device; - hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); - -#ifdef CONFIG_MPC83xx_PCI2 - hose2 = pcibios_alloc_controller(); - if(!hose2) - return; - - hose2->bus_offset = hose1->last_busno + 1; - hose2->first_busno = hose1->last_busno + 1; - hose2->last_busno = 0xff; - setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, - binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); - hose2->set_cfg_type = 1; - - mpc83xx_setup_pci2(hose2); - - hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; - hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; - hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; - - hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; - hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; - hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; - hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); - /* setup resources */ - pci_init_resource(&hose2->io_resource, - MPC83xx_PCI2_LOWER_IO, - MPC83xx_PCI2_UPPER_IO, - IORESOURCE_IO, "PCI host bridge 2"); - pci_init_resource(&hose2->mem_resources[0], - MPC83xx_PCI2_LOWER_MEM, - MPC83xx_PCI2_UPPER_MEM, - IORESOURCE_MEM, "PCI host bridge 2"); - - hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); -#endif /* CONFIG_MPC83xx_PCI2 */ -} -#endif /*CONFIG_PCI*/ diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h deleted file mode 100644 index b918a2d245e..00000000000 --- a/arch/ppc/syslib/ppc83xx_setup.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * MPC83XX common board definitions - * - * Maintainer: Kumar Gala - * - * Copyright 2005 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H -#define __PPC_SYSLIB_PPC83XX_SETUP_H - -#include - -extern unsigned long mpc83xx_find_end_of_memory(void) __init; -extern long mpc83xx_time_init(void) __init; -extern void mpc83xx_calibrate_decr(void) __init; -extern void mpc83xx_early_serial_map(void) __init; -extern void mpc83xx_restart(char *cmd); -extern void mpc83xx_power_off(void); -extern void mpc83xx_halt(void); -extern void mpc83xx_setup_hose(void) __init; - -/* PCI config */ -#define PCI1_CFG_ADDR_OFFSET (0x8300) -#define PCI1_CFG_DATA_OFFSET (0x8304) - -#define PCI2_CFG_ADDR_OFFSET (0x8380) -#define PCI2_CFG_DATA_OFFSET (0x8384) - -/* Serial Config */ -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 2 -#endif - -#ifndef BASE_BAUD -#define BASE_BAUD 115200 -#endif - -#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */ -- cgit v1.2.3