From 73505b445dbb8ad12df468404c4dd5cde9c40c65 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Sun, 12 Aug 2007 15:26:12 +0900 Subject: sh: intc - rework core code This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/cchips/voyagergx/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/sh/cchips') diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c index 0ca405a46a5..2d3620cc92b 100644 --- a/arch/sh/cchips/voyagergx/irq.c +++ b/arch/sh/cchips/voyagergx/irq.c @@ -50,7 +50,7 @@ static struct intc_vect vectors[] = { }; static struct intc_mask_reg mask_registers[] = { - { VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ + { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ { UP, G54, G53, G52, G51, G50, G49, G48, I2C, PW, 0, DMA, PCI, I2S, AC, US, 0, 0, U1, U0, CV, MC, S1, S0, -- cgit v1.2.3