From 7639a4541f7e7abb1295ff8ab39cc2f5842239ae Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Oct 2008 13:02:48 +0900 Subject: sh: Migrate common board headers to mach-common/. Signed-off-by: Paul Mundt --- arch/sh/include/mach-common/mach/edosk7705.h | 30 ++++ arch/sh/include/mach-common/mach/highlander.h | 198 ++++++++++++++++++++++++ arch/sh/include/mach-common/mach/hp6xx.h | 58 +++++++ arch/sh/include/mach-common/mach/lboxre2.h | 27 ++++ arch/sh/include/mach-common/mach/magicpanelr2.h | 67 ++++++++ arch/sh/include/mach-common/mach/microdev.h | 80 ++++++++++ arch/sh/include/mach-common/mach/migor.h | 64 ++++++++ arch/sh/include/mach-common/mach/r2d.h | 70 +++++++++ arch/sh/include/mach-common/mach/sdk7780.h | 81 ++++++++++ arch/sh/include/mach-common/mach/sh7763rdp.h | 54 +++++++ arch/sh/include/mach-common/mach/sh7785lcr.h | 55 +++++++ arch/sh/include/mach-common/mach/shmin.h | 9 ++ arch/sh/include/mach-common/mach/snapgear.h | 71 +++++++++ arch/sh/include/mach-common/mach/systemh7751.h | 71 +++++++++ arch/sh/include/mach-common/mach/titan.h | 17 ++ 15 files changed, 952 insertions(+) create mode 100644 arch/sh/include/mach-common/mach/edosk7705.h create mode 100644 arch/sh/include/mach-common/mach/highlander.h create mode 100644 arch/sh/include/mach-common/mach/hp6xx.h create mode 100644 arch/sh/include/mach-common/mach/lboxre2.h create mode 100644 arch/sh/include/mach-common/mach/magicpanelr2.h create mode 100644 arch/sh/include/mach-common/mach/microdev.h create mode 100644 arch/sh/include/mach-common/mach/migor.h create mode 100644 arch/sh/include/mach-common/mach/r2d.h create mode 100644 arch/sh/include/mach-common/mach/sdk7780.h create mode 100644 arch/sh/include/mach-common/mach/sh7763rdp.h create mode 100644 arch/sh/include/mach-common/mach/sh7785lcr.h create mode 100644 arch/sh/include/mach-common/mach/shmin.h create mode 100644 arch/sh/include/mach-common/mach/snapgear.h create mode 100644 arch/sh/include/mach-common/mach/systemh7751.h create mode 100644 arch/sh/include/mach-common/mach/titan.h (limited to 'arch/sh/include/mach-common') diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h new file mode 100644 index 00000000000..5bdc9d9be3d --- /dev/null +++ b/arch/sh/include/mach-common/mach/edosk7705.h @@ -0,0 +1,30 @@ +/* + * include/asm-sh/edosk7705.h + * + * Modified version of io_se.h for the EDOSK7705 specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Hitachi EDOSK7705 development board + */ + +#ifndef __ASM_SH_EDOSK7705_IO_H +#define __ASM_SH_EDOSK7705_IO_H + +#include + +extern unsigned char sh_edosk7705_inb(unsigned long port); +extern unsigned int sh_edosk7705_inl(unsigned long port); + +extern void sh_edosk7705_outb(unsigned char value, unsigned long port); +extern void sh_edosk7705_outl(unsigned int value, unsigned long port); + +extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count); +extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count); +extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset); + +#endif /* __ASM_SH_EDOSK7705_IO_H */ diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h new file mode 100644 index 00000000000..306f7359f7d --- /dev/null +++ b/arch/sh/include/mach-common/mach/highlander.h @@ -0,0 +1,198 @@ +#ifndef __ASM_SH_RENESAS_R7780RP_H +#define __ASM_SH_RENESAS_R7780RP_H + +/* Box specific addresses. */ +#if defined(CONFIG_SH_R7780MP) +#define PA_BCR 0xa4000000 /* FPGA */ +#define PA_SDPOW (-1) + +#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ +#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ +#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */ +#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */ +#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */ +#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */ +#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */ +#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */ +#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */ +#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */ +#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */ +#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */ +#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */ +#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */ +#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */ +#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */ +#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ +#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ +#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ +#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ +#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ +#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */ +#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ +#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ +#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ +#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */ +#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */ +#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */ +#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */ +#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */ +#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */ +#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */ +#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */ +#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */ +#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */ +#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */ +#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */ +#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */ +#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */ +#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */ +#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */ +#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */ +#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */ +#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */ +#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */ +#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */ +#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */ +#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */ +#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */ +#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */ +#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */ +#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */ +#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */ +#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */ +#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */ +#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */ +#define PA_PMR (PA_BCR+0x0900) /* */ + +#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ +#define IVDR_CK_ON 8 /* iVDR Clock ON */ + +#elif defined(CONFIG_SH_R7780RP) +#define PA_POFF (-1) + +#define PA_BCR 0xa5000000 /* FPGA */ +#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */ +#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */ +#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */ +#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */ +#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */ +#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */ +#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */ +#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */ +#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */ +#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */ +#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */ +#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */ +#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */ +#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */ +#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */ +#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */ +#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */ +#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */ +#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */ +#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */ +#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */ +#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */ +#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */ +#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */ +#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */ +#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */ +#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */ +#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */ +#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */ +#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */ +#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */ +#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */ +#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */ +#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */ +#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */ +#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */ +#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */ +#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */ +#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */ +#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */ +#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */ +#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */ + +#define PA_AX88796L 0xa5800400 /* AX88796L Area */ +#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */ +#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ +#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ + +#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ + +#define IVDR_CK_ON 8 /* iVDR Clock ON */ + +#elif defined(CONFIG_SH_R7785RP) +#define PA_BCR 0xa4000000 /* FPGA */ +#define PA_SDPOW (-1) + +#define PA_PCISCR (PA_BCR+0x0000) +#define PA_IRLPRA (PA_BCR+0x0002) +#define PA_IRLPRB (PA_BCR+0x0004) +#define PA_IRLPRC (PA_BCR+0x0006) +#define PA_IRLPRD (PA_BCR+0x0008) +#define IRLCNTR1 (PA_BCR+0x0010) +#define PA_IRLPRE (PA_BCR+0x000a) +#define PA_IRLPRF (PA_BCR+0x000c) +#define PA_EXIRLCR (PA_BCR+0x000e) +#define PA_IRLMCR1 (PA_BCR+0x0010) +#define PA_IRLMCR2 (PA_BCR+0x0012) +#define PA_IRLSSR1 (PA_BCR+0x0014) +#define PA_IRLSSR2 (PA_BCR+0x0016) +#define PA_CFTCR (PA_BCR+0x0100) +#define PA_CFPCR (PA_BCR+0x0102) +#define PA_PCICR (PA_BCR+0x0110) +#define PA_IVDRCTL (PA_BCR+0x0112) +#define PA_IVDRSR (PA_BCR+0x0114) +#define PA_PDRSTCR (PA_BCR+0x0116) +#define PA_POFF (PA_BCR+0x0120) +#define PA_LCDCR (PA_BCR+0x0130) +#define PA_TPCR (PA_BCR+0x0140) +#define PA_TPCKCR (PA_BCR+0x0142) +#define PA_TPRSTR (PA_BCR+0x0144) +#define PA_TPXPDR (PA_BCR+0x0146) +#define PA_TPYPDR (PA_BCR+0x0148) +#define PA_GPIOPFR (PA_BCR+0x0150) +#define PA_GPIODR (PA_BCR+0x0152) +#define PA_OBLED (PA_BCR+0x0154) +#define PA_SWSR (PA_BCR+0x0156) +#define PA_VERREG (PA_BCR+0x0158) +#define PA_SMCR (PA_BCR+0x0200) +#define PA_SMSMADR (PA_BCR+0x0202) +#define PA_SMMR (PA_BCR+0x0204) +#define PA_SMSADR1 (PA_BCR+0x0206) +#define PA_SMSADR32 (PA_BCR+0x0244) +#define PA_SMTRDR1 (PA_BCR+0x0246) +#define PA_SMTRDR16 (PA_BCR+0x0264) +#define PA_CU3MDR (PA_BCR+0x0300) +#define PA_CU5MDR (PA_BCR+0x0302) +#define PA_MMSR (PA_BCR+0x0400) + +#define IVDR_CK_ON 4 /* iVDR Clock ON */ +#endif + +#define HL_FPGA_IRQ_BASE 200 +#define HL_NR_IRL 15 + +#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) +#define IRQ_CF (HL_FPGA_IRQ_BASE + 1) +#define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) +#define IRQ_EXT0 (HL_FPGA_IRQ_BASE + 3) +#define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 4) +#define IRQ_EXT2 (HL_FPGA_IRQ_BASE + 5) +#define IRQ_EXT3 (HL_FPGA_IRQ_BASE + 6) +#define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 7) +#define IRQ_EXT5 (HL_FPGA_IRQ_BASE + 8) +#define IRQ_EXT6 (HL_FPGA_IRQ_BASE + 9) +#define IRQ_EXT7 (HL_FPGA_IRQ_BASE + 10) +#define IRQ_SMBUS (HL_FPGA_IRQ_BASE + 11) +#define IRQ_TP (HL_FPGA_IRQ_BASE + 12) +#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13) +#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14) +#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15) +#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16) + +unsigned char *highlander_plat_irq_setup(void); + +#endif /* __ASM_SH_RENESAS_R7780RP */ diff --git a/arch/sh/include/mach-common/mach/hp6xx.h b/arch/sh/include/mach-common/mach/hp6xx.h new file mode 100644 index 00000000000..0d4165a32dc --- /dev/null +++ b/arch/sh/include/mach-common/mach/hp6xx.h @@ -0,0 +1,58 @@ +#ifndef __ASM_SH_HP6XX_H +#define __ASM_SH_HP6XX_H + +/* + * Copyright (C) 2003, 2004, 2005 Andriy Skulysh + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#define HP680_BTN_IRQ 32 /* IRQ0_IRQ */ +#define HP680_TS_IRQ 35 /* IRQ3_IRQ */ +#define HP680_HD64461_IRQ 36 /* IRQ4_IRQ */ + +#define DAC_LCD_BRIGHTNESS 0 +#define DAC_SPEAKER_VOLUME 1 + +#define PGDR_OPENED 0x01 +#define PGDR_MAIN_BATTERY_OUT 0x04 +#define PGDR_PLAY_BUTTON 0x08 +#define PGDR_REWIND_BUTTON 0x10 +#define PGDR_RECORD_BUTTON 0x20 + +#define PHDR_TS_PEN_DOWN 0x08 + +#define PJDR_LED_BLINK 0x02 + +#define PKDR_LED_GREEN 0x10 + +#define SCPDR_TS_SCAN_ENABLE 0x20 +#define SCPDR_TS_SCAN_Y 0x02 +#define SCPDR_TS_SCAN_X 0x01 + +#define SCPCR_TS_ENABLE 0x405 +#define SCPCR_TS_MASK 0xc0f + +#define ADC_CHANNEL_TS_Y 1 +#define ADC_CHANNEL_TS_X 2 +#define ADC_CHANNEL_BATTERY 3 +#define ADC_CHANNEL_BACKUP 4 +#define ADC_CHANNEL_CHARGE 5 + +#define HD64461_GPADR_SPEAKER 0x01 +#define HD64461_GPADR_PCMCIA0 (0x02|0x08) + +#define HD64461_GPBDR_LCDOFF 0x01 +#define HD64461_GPBDR_LCD_CONTRAST_MASK 0x78 +#define HD64461_GPBDR_LED_RED 0x80 + +#include +#include + +#define PJDR 0xa4000130 +#define PKDR 0xa4000132 + +#endif /* __ASM_SH_HP6XX_H */ diff --git a/arch/sh/include/mach-common/mach/lboxre2.h b/arch/sh/include/mach-common/mach/lboxre2.h new file mode 100644 index 00000000000..e6d16050492 --- /dev/null +++ b/arch/sh/include/mach-common/mach/lboxre2.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SH_LBOXRE2_H +#define __ASM_SH_LBOXRE2_H + +/* + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * NTT COMWARE L-BOX RE2 support + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#define IRQ_CF1 9 /* CF1 */ +#define IRQ_CF0 10 /* CF0 */ +#define IRQ_INTD 11 /* INTD */ +#define IRQ_ETH1 12 /* Ether1 */ +#define IRQ_ETH0 13 /* Ether0 */ +#define IRQ_INTA 14 /* INTA */ + +void init_lboxre2_IRQ(void); + +#define __IO_PREFIX lboxre2 +#include + +#endif /* __ASM_SH_LBOXRE2_H */ diff --git a/arch/sh/include/mach-common/mach/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h new file mode 100644 index 00000000000..c644a77ee35 --- /dev/null +++ b/arch/sh/include/mach-common/mach/magicpanelr2.h @@ -0,0 +1,67 @@ +/* + * include/asm-sh/magicpanelr2.h + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * I/O addresses and bitmasks for Magic Panel Release 2 board + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_SH_MAGICPANELR2_H +#define __ASM_SH_MAGICPANELR2_H + +#include + +#define __IO_PREFIX mpr2 +#include + + +#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg) +#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg) +#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg) +#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg) +#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg) +#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg) + + +#define PA_LED PORT_PADR /* LED */ + + +/* BSC */ +#define CMNCR 0xA4FD0000UL +#define CS0BCR 0xA4FD0004UL +#define CS2BCR 0xA4FD0008UL +#define CS3BCR 0xA4FD000CUL +#define CS4BCR 0xA4FD0010UL +#define CS5ABCR 0xA4FD0014UL +#define CS5BBCR 0xA4FD0018UL +#define CS6ABCR 0xA4FD001CUL +#define CS6BBCR 0xA4FD0020UL +#define CS0WCR 0xA4FD0024UL +#define CS2WCR 0xA4FD0028UL +#define CS3WCR 0xA4FD002CUL +#define CS4WCR 0xA4FD0030UL +#define CS5AWCR 0xA4FD0034UL +#define CS5BWCR 0xA4FD0038UL +#define CS6AWCR 0xA4FD003CUL +#define CS6BWCR 0xA4FD0040UL + + +/* usb */ + +#define PORT_UTRCTL 0xA405012CUL +#define PORT_UCLKCR_W 0xA40A0008UL + +#define INTC_ICR0 0xA414FEE0UL +#define INTC_ICR1 0xA4140010UL +#define INTC_ICR2 0xA4140012UL + +/* MTD */ + +#define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL +#define MPR2_MTD_KERNEL_SIZE 0x00200000UL + +#endif /* __ASM_SH_MAGICPANELR2_H */ diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h new file mode 100644 index 00000000000..1aed15856e1 --- /dev/null +++ b/arch/sh/include/mach-common/mach/microdev.h @@ -0,0 +1,80 @@ +/* + * linux/include/asm-sh/microdev.h + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * + * Definitions for the SuperH SH4-202 MicroDev board. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ +#ifndef __ASM_SH_MICRODEV_H +#define __ASM_SH_MICRODEV_H + +extern void init_microdev_irq(void); +extern void microdev_print_fpga_intc_status(void); + +/* + * The following are useful macros for manipulating the interrupt + * controller (INTC) on the CPU-board FPGA. should be noted that there + * is an INTC on the FPGA, and a separate INTC on the SH4-202 core - + * these are two different things, both of which need to be prorammed to + * correctly route - unfortunately, they have the same name and + * abbreviations! + */ +#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ +#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */ +#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ +#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ + + +/* + * The following are the IRQ numbers for the Linux Kernel for external + * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. + */ +#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ +#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ +#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ +#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ +#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ +#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ +#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ +#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ + +/* + * The following are the IRQ numbers for the INTC on the FPGA for + * external interrupts. i.e. the bits in the INTC registers in the + * FPGA. + */ +#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ +#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ +#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ +#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ +#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ +#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ +#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ +#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ + +#define MICRODEV_IRQ_PCI_INTA 8 +#define MICRODEV_IRQ_PCI_INTB 9 +#define MICRODEV_IRQ_PCI_INTC 10 +#define MICRODEV_IRQ_PCI_INTD 11 + +#define __IO_PREFIX microdev +#include + +#if defined(CONFIG_PCI) +unsigned char microdev_pci_inb(unsigned long port); +unsigned short microdev_pci_inw(unsigned long port); +unsigned long microdev_pci_inl(unsigned long port); +void microdev_pci_outb(unsigned char data, unsigned long port); +void microdev_pci_outw(unsigned short data, unsigned long port); +void microdev_pci_outl(unsigned long data, unsigned long port); +#endif + +#endif /* __ASM_SH_MICRODEV_H */ diff --git a/arch/sh/include/mach-common/mach/migor.h b/arch/sh/include/mach-common/mach/migor.h new file mode 100644 index 00000000000..e451f0229e0 --- /dev/null +++ b/arch/sh/include/mach-common/mach/migor.h @@ -0,0 +1,64 @@ +#ifndef __ASM_SH_MIGOR_H +#define __ASM_SH_MIGOR_H + +/* + * linux/include/asm-sh/migor.h + * + * Copyright (C) 2008 Renesas Solutions + * + * Portions Copyright (C) 2007 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include + +/* GPIO */ +#define PORT_PACR 0xa4050100 +#define PORT_PDCR 0xa4050106 +#define PORT_PECR 0xa4050108 +#define PORT_PHCR 0xa405010e +#define PORT_PJCR 0xa4050110 +#define PORT_PKCR 0xa4050112 +#define PORT_PLCR 0xa4050114 +#define PORT_PMCR 0xa4050116 +#define PORT_PRCR 0xa405011c +#define PORT_PTCR 0xa4050140 +#define PORT_PUCR 0xa4050142 +#define PORT_PVCR 0xa4050144 +#define PORT_PWCR 0xa4050146 +#define PORT_PXCR 0xa4050148 +#define PORT_PYCR 0xa405014a +#define PORT_PZCR 0xa405014c +#define PORT_PADR 0xa4050120 +#define PORT_PHDR 0xa405012e +#define PORT_PTDR 0xa4050160 +#define PORT_PWDR 0xa4050166 + +#define PORT_HIZCRA 0xa4050158 +#define PORT_HIZCRC 0xa405015c + +#define PORT_MSELCRB 0xa4050182 + +#define PORT_PSELA 0xa405014e +#define PORT_PSELB 0xa4050150 +#define PORT_PSELC 0xa4050152 +#define PORT_PSELD 0xa4050154 +#define PORT_PSELE 0xa4050156 + +#define PORT_HIZCRA 0xa4050158 +#define PORT_HIZCRB 0xa405015a +#define PORT_HIZCRC 0xa405015c + +#define BSC_CS4BCR 0xfec10010 +#define BSC_CS6ABCR 0xfec1001c +#define BSC_CS4WCR 0xfec10030 + +#include