From de7ca2144c36291a491bd39afad172f56432a4bb Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 19 Feb 2010 09:12:00 +0000 Subject: sh: clock-cpg div4 set_rate() shift fix Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate(). Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/clock-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/sh/kernel/cpu') diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 2827abb5d2a..72a5e621a9b 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c @@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id return idx; value = __raw_readl(clk->enable_reg); - value &= ~0xf; - value |= idx; + value &= ~(0xf << clk->enable_bit); + value |= (idx << clk->enable_bit); __raw_writel(value, clk->enable_reg); return 0; -- cgit v1.2.3