From 6503fe4a6508673c15a509ec4ac3ca5979ae9593 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Thu, 20 Aug 2009 13:27:44 +0900 Subject: sh: Better description of SH-4 PTEA register update. Signed-off-by: Michael Trimarchi Signed-off-by: Paul Mundt --- arch/sh/mm/tlb-sh4.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index f0c7b7397fa..fd0d11f1a81 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c @@ -61,9 +61,12 @@ void update_mmu_cache(struct vm_area_struct * vma, */ ctrl_outl(pte.pte_high, MMU_PTEA); #else - if (cpu_data->flags & CPU_HAS_PTEA) - /* TODO: make this look less hacky */ - ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); + if (cpu_data->flags & CPU_HAS_PTEA) { + /* The last 3 bits and the first one of pteval contains + * the PTEA timing control and space attribute bits + */ + ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA); + } #endif /* Set PTEL register */ -- cgit v1.2.3 From c01f0f1a4a96eb3acc5850e18cc43f24366966d0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 21 Aug 2009 16:30:28 +0900 Subject: sh: Add initial support for SH7757 CPU subtype Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/mm/Kconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 2795618e4f0..64dc1ad5980 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -82,7 +82,7 @@ config 32BIT config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT default y help @@ -97,7 +97,7 @@ choice config PMB bool "PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT help If you say Y here, physical addressing will be extended to @@ -106,7 +106,8 @@ config PMB config PMB_FIXED bool "fixed PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \ + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \ + CPU_SUBTYPE_SH7780 || \ CPU_SUBTYPE_SH7785) select 32BIT help -- cgit v1.2.3 From a5cf9e2444ec15de5407696ff21c32dd21ca0a8d Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Mon, 24 Aug 2009 17:36:24 +0900 Subject: sh: Improve comments int SH4 cache flushing code This is a pure documentation, to try to explain why the cache flushing code for the SH4 is implemented the way it is. Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/mm/cache-sh4.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 5cfe08dbb59..7ce81618831 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -581,6 +581,17 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, * Break the 1, 2 and 4 way variants of this out into separate functions to * avoid nearly all the overhead of having the conditional stuff in the function * bodies (+ the 1 and 2 way cases avoid saving any registers too). + * + * We want to eliminate unnecessary bus transactions, so this code uses + * a non-obvious technique. + * + * Loop over a cache way sized block of, one cache line at a time. For each + * line, use movca.a to cause the current cache line contents to be written + * back, but without reading anything from main memory. However this has the + * side effect that the cache is now caching that memory location. So follow + * this with a cache invalidate to mark the cache line invalid. And do all + * this with interrupts disabled, to avoid the cache line being accidently + * evicted while it is holding garbage. */ static void __flush_dcache_segment_1way(unsigned long start, unsigned long extent_per_way) -- cgit v1.2.3 From a1fce732359b80ead84efba23059a5f1b572b85a Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Mon, 24 Aug 2009 18:29:25 +0900 Subject: sh: Fix overzealous checking in __ioremap() Allow peripherals before the start of RAM to be remapped. Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/mm/ioremap_32.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c index da2f4186f2c..c3250614e3a 100644 --- a/arch/sh/mm/ioremap_32.c +++ b/arch/sh/mm/ioremap_32.c @@ -57,14 +57,6 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size, if (is_pci_memory_fixed_range(phys_addr, size)) return (void __iomem *)phys_addr; -#if !defined(CONFIG_PMB_FIXED) - /* - * Don't allow anybody to remap normal RAM that we're using.. - */ - if (phys_addr < virt_to_phys(high_memory)) - return NULL; -#endif - /* * Mappings have to be page-aligned */ -- cgit v1.2.3 From ffad9d7a54a5e809007135595c778715aa0fb07a Mon Sep 17 00:00:00 2001 From: Stuart Menefy Date: Mon, 24 Aug 2009 18:39:39 +0900 Subject: sh: Fix problems with cache flushing when cache is in write-through mode Change the method used to flush the cache in write-through mode to avoid corrupted data being written back to memory. Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt --- arch/sh/mm/cache-sh4.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 7ce81618831..397c1030c7a 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -592,6 +592,20 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, * this with a cache invalidate to mark the cache line invalid. And do all * this with interrupts disabled, to avoid the cache line being accidently * evicted while it is holding garbage. + * + * This also breaks in a number of circumstances: + * - if there are modifications to the region of memory just above + * empty_zero_page (for example because a breakpoint has been placed + * there), then these can be lost. + * + * This is because the the memory address which the cache temporarily + * caches in the above description is empty_zero_page. So the + * movca.l hits the cache (it is assumed that it misses, or at least + * isn't dirty), modifies the line and then invalidates it, losing the + * required change. + * + * - If caches are disabled or configured in write-through mode, then + * the movca.l writes garbage directly into memory. */ static void __flush_dcache_segment_1way(unsigned long start, unsigned long extent_per_way) @@ -641,6 +655,25 @@ static void __flush_dcache_segment_1way(unsigned long start, } while (a0 < a0e); } +#ifdef CONFIG_CACHE_WRITETHROUGH +/* This method of cache flushing avoids the problems discussed + * in the comment above if writethrough caches are enabled. */ +static void __flush_dcache_segment_2way(unsigned long start, + unsigned long extent_per_way) +{ + unsigned long array_addr; + + array_addr = CACHE_OC_ADDRESS_ARRAY | + (start & cpu_data->dcache.entry_mask); + + while (extent_per_way) { + ctrl_outl(0, array_addr); + ctrl_outl(0, array_addr + cpu_data->dcache.way_incr); + array_addr += cpu_data->dcache.linesz; + extent_per_way -= cpu_data->dcache.linesz; + } +} +#else static void __flush_dcache_segment_2way(unsigned long start, unsigned long extent_per_way) { @@ -699,6 +732,7 @@ static void __flush_dcache_segment_2way(unsigned long start, a1 += linesz; } while (a0 < a0e); } +#endif static void __flush_dcache_segment_4way(unsigned long start, unsigned long extent_per_way) -- cgit v1.2.3 From ce3f7cb96e67d6518c7fc7b361a76409c3817d64 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Tue, 1 Sep 2009 13:32:48 +0900 Subject: sh: Fix dcache flushing for N-way write-through caches. This adopts the special-cased 2-way write-through dcache flusher for N-ways and moves it in to the generic path. Assignment is done at runtime via the check for the CCR_CACHE_WT bit in the same path as the per-way writeback flushers. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt --- arch/sh/mm/cache-sh4.c | 48 +++++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 21 deletions(-) (limited to 'arch/sh/mm') diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 397c1030c7a..b36a9c986a5 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -25,13 +25,14 @@ #define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */ #define MAX_ICACHE_PAGES 32 +static void __flush_dcache_segment_writethrough(unsigned long start, + unsigned long extent); static void __flush_dcache_segment_1way(unsigned long start, unsigned long extent); static void __flush_dcache_segment_2way(unsigned long start, unsigned long extent); static void __flush_dcache_segment_4way(unsigned long start, unsigned long extent); - static void __flush_cache_4096(unsigned long addr, unsigned long phys, unsigned long exec_offset); @@ -95,10 +96,17 @@ static void __init emit_cache_params(void) */ void __init p3_cache_init(void) { + unsigned int wt_enabled = !!(__raw_readl(CCR) & CCR_CACHE_WT); + compute_alias(&boot_cpu_data.icache); compute_alias(&boot_cpu_data.dcache); compute_alias(&boot_cpu_data.scache); + if (wt_enabled) { + __flush_dcache_segment_fn = __flush_dcache_segment_writethrough; + goto out; + } + switch (boot_cpu_data.dcache.ways) { case 1: __flush_dcache_segment_fn = __flush_dcache_segment_1way; @@ -114,6 +122,7 @@ void __init p3_cache_init(void) break; } +out: emit_cache_params(); } @@ -607,6 +616,23 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, * - If caches are disabled or configured in write-through mode, then * the movca.l writes garbage directly into memory. */ +static void __flush_dcache_segment_writethrough(unsigned long start, + unsigned long extent_per_way) +{ + unsigned long addr; + int i; + + addr = CACHE_OC_ADDRESS_ARRAY | (start & cpu_data->dcache.entry_mask); + + while (extent_per_way) { + for (i = 0; i < cpu_data->dcache.ways; i++) + __raw_writel(0, addr + cpu_data->dcache.way_incr * i); + + addr += cpu_data->dcache.linesz; + extent_per_way -= cpu_data->dcache.linesz; + } +} + static void __flush_dcache_segment_1way(unsigned long start, unsigned long extent_per_way) { @@ -655,25 +681,6 @@ static void __flush_dcache_segment_1way(unsigned long start, } while (a0 < a0e); } -#ifdef CONFIG_CACHE_WRITETHROUGH -/* This method of cache flushing avoids the problems discussed - * in the comment above if writethrough caches are enabled. */ -static void __flush_dcache_segment_2way(unsigned long start, - unsigned long extent_per_way) -{ - unsigned long array_addr; - - array_addr = CACHE_OC_ADDRESS_ARRAY | - (start & cpu_data->dcache.entry_mask); - - while (extent_per_way) { - ctrl_outl(0, array_addr); - ctrl_outl(0, array_addr + cpu_data->dcache.way_incr); - array_addr += cpu_data->dcache.linesz; - extent_per_way -= cpu_data->dcache.linesz; - } -} -#else static void __flush_dcache_segment_2way(unsigned long start, unsigned long extent_per_way) { @@ -732,7 +739,6 @@ static void __flush_dcache_segment_2way(unsigned long start, a1 += linesz; } while (a0 < a0e); } -#endif static void __flush_dcache_segment_4way(unsigned long start, unsigned long extent_per_way) -- cgit v1.2.3