From 0949be35095b53dbaa72db700cb5074c5c249629 Mon Sep 17 00:00:00 2001
From: Simon Arlott <simon@arlott.org>
Date: Wed, 2 May 2007 19:27:05 +0200
Subject: [PATCH] i386: Add an option for the VIA C7 which sets appropriate L1
 cache

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
a cache line length of 64 according to
http://www.digit-life.com/articles2/cpu/rmma-via-c7.html.  This patch sets
gcc to -march=686 and select s the correct cache shift.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Andi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@suse.de>
Cc: Dave Jones <davej@codemonkey.org.uk>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
 arch/um/defconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'arch/um/defconfig')

diff --git a/arch/um/defconfig b/arch/um/defconfig
index 780cc0a4a12..f938fa82214 100644
--- a/arch/um/defconfig
+++ b/arch/um/defconfig
@@ -41,6 +41,7 @@ CONFIG_M686=y
 # CONFIG_MGEODE_LX is not set
 # CONFIG_MCYRIXIII is not set
 # CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
 # CONFIG_X86_GENERIC is not set
 CONFIG_X86_CMPXCHG=y
 CONFIG_X86_XADD=y
-- 
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