From 6bee00dbbcb1e9feb0510e9a7104b4af00adc574 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Fri, 24 Oct 2008 10:21:45 -0700 Subject: [ARM] xsc3: revert writethrough memory-type encoding change Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was fingered by git-bisect for a boot failure on iop13xx. The change made L_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that this mapping is used for the vector page. Given the regression, and the fact this page is used often, restore the old behaviour. Signed-off-by: Dan Williams --- arch/arm/mm/proc-xsc3.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 04dc8b65401..8f6cf56c11c 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -349,7 +349,7 @@ ENTRY(cpu_xsc3_switch_mm) cpu_xsc3_mt_table: .long 0x00 @ L_PTE_MT_UNCACHED .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE - .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH + .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED .long 0x00 @ unused -- cgit v1.2.3 From 3b15e581981b3ad35809f56d8131d5c19b6da1bd Mon Sep 17 00:00:00 2001 From: Fenghua Yu Date: Thu, 23 Oct 2008 16:51:00 -0700 Subject: x86/PCI: build failure at x86/kernel/pci-dma.c with !CONFIG_PCI On Thu, Oct 23, 2008 at 04:09:52PM -0700, Alexander Beregalov wrote: > arch/x86/kernel/built-in.o: In function `iommu_setup': > pci-dma.c:(.init.text+0x36ad): undefined reference to `forbid_dac' > pci-dma.c:(.init.text+0x36cc): undefined reference to `forbid_dac' > pci-dma.c:(.init.text+0x3711): undefined reference to `forbid_dac This patch partially reverts a patch to add IOMMU support to ia64. The forbid_dac variable was incorrectly moved to quirks.c, which isn't built when PCI is disabled. Tested-by: "Alexander Beregalov" Acked-by: FUJITA Tomonori Signed-off-by: Fenghua Yu Signed-off-by: Jesse Barnes --- arch/ia64/include/asm/iommu.h | 1 - arch/ia64/kernel/pci-dma.c | 7 ------- arch/x86/include/asm/iommu.h | 1 - arch/x86/kernel/pci-dma.c | 16 ++++++++++++++++ 4 files changed, 16 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 5fb2bb93de3..0490794fe4a 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -11,6 +11,5 @@ extern int force_iommu, no_iommu; extern int iommu_detected; extern void iommu_dma_init(void); extern void machvec_init(const char *name); -extern int forbid_dac; #endif diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c index 10a75b55765..031abbf9c87 100644 --- a/arch/ia64/kernel/pci-dma.c +++ b/arch/ia64/kernel/pci-dma.c @@ -89,13 +89,6 @@ int iommu_dma_supported(struct device *dev, u64 mask) { struct dma_mapping_ops *ops = get_dma_ops(dev); -#ifdef CONFIG_PCI - if (mask > 0xffffffff && forbid_dac > 0) { - dev_info(dev, "Disallowing DAC for device\n"); - return 0; - } -#endif - if (ops->dma_supported_op) return ops->dma_supported_op(dev, mask); diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index 98e28ea8cd1..e4a552d4446 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -7,7 +7,6 @@ extern struct dma_mapping_ops nommu_dma_ops; extern int force_iommu, no_iommu; extern int iommu_detected; extern int dmar_disabled; -extern int forbid_dac; extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len); diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index 1972266e8ba..19262482021 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -9,6 +9,8 @@ #include #include +static int forbid_dac __read_mostly; + struct dma_mapping_ops *dma_ops; EXPORT_SYMBOL(dma_ops); @@ -291,3 +293,17 @@ void pci_iommu_shutdown(void) } /* Must execute after PCI subsystem */ fs_initcall(pci_iommu_init); + +#ifdef CONFIG_PCI +/* Many VIA bridges seem to corrupt data for DAC. Disable it here */ + +static __devinit void via_no_dac(struct pci_dev *dev) +{ + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) { + printk(KERN_INFO "PCI: VIA PCI bridge detected." + "Disabling DAC.\n"); + forbid_dac = 1; + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac); +#endif -- cgit v1.2.3 From 531f6ed7de911e975352fbb2b228367121da630a Mon Sep 17 00:00:00 2001 From: Markus Metzger Date: Fri, 17 Oct 2008 09:09:27 +0200 Subject: x86, bts: improve help text for BTS config Improve the help text of the X86_PTRACE_BTS config. Make X86_DS invisible and depend on X86_PTRACE_BTS. Reported-by: Roland Dreier Signed-off-by: Markus Metzger Signed-off-by: Ingo Molnar --- arch/x86/Kconfig.cpu | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 0b7c4a3f065..b815664fe37 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -513,19 +513,19 @@ config CPU_SUP_UMC_32 If unsure, say N. config X86_DS - bool "Debug Store support" - default y - help - Add support for Debug Store. - This allows the kernel to provide a memory buffer to the hardware - to store various profiling and tracing events. + def_bool X86_PTRACE_BTS + depends on X86_DEBUGCTLMSR config X86_PTRACE_BTS - bool "ptrace interface to Branch Trace Store" + bool "Branch Trace Store" default y - depends on (X86_DS && X86_DEBUGCTLMSR) + depends on X86_DEBUGCTLMSR help - Add a ptrace interface to allow collecting an execution trace - of the traced task. - This collects control flow changes in a (cyclic) buffer and allows - debuggers to fill in the gaps and show an execution trace of the debuggee. + This adds a ptrace interface to the hardware's branch trace store. + + Debuggers may use it to collect an execution trace of the debugged + application in order to answer the question 'how did I get here?'. + Debuggers may trace user mode as well as kernel mode. + + Say Y unless there is no application development on this machine + and you want to save a small amount of code size. -- cgit v1.2.3 From 36b75da27bb51dc34e358d0b7487406132806c46 Mon Sep 17 00:00:00 2001 From: Peter Oruba Date: Fri, 17 Oct 2008 15:30:37 +0200 Subject: x86: microcode patch loader author update Removed one author's email address from module init message. Signed-off-by: Peter Oruba Signed-off-by: Ingo Molnar --- arch/x86/kernel/microcode_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 936d8d55f23..82fb2809ce3 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -480,8 +480,8 @@ static int __init microcode_init(void) printk(KERN_INFO "Microcode Update Driver: v" MICROCODE_VERSION - " " - " \n"); + " ," + " Peter Oruba\n"); return 0; } -- cgit v1.2.3 From 3c52204bb90834bca8e9e78a3628d886ad6d4db5 Mon Sep 17 00:00:00 2001 From: Peter Oruba Date: Fri, 17 Oct 2008 15:30:38 +0200 Subject: x86: AMD microcode patch loader author update Removed author's email address from MODULE_AUTHOR. Signed-off-by: Peter Oruba Signed-off-by: Ingo Molnar --- arch/x86/kernel/microcode_amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 7a1f8eeac2c..5f8e5d75a25 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c @@ -39,7 +39,7 @@ #include MODULE_DESCRIPTION("AMD Microcode Update Driver"); -MODULE_AUTHOR("Peter Oruba "); +MODULE_AUTHOR("Peter Oruba"); MODULE_LICENSE("GPL v2"); #define UCODE_MAGIC 0x00414d44 -- cgit v1.2.3 From 1281675e9c0d4d42d993697f4daab45ef22d49da Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Tue, 14 Oct 2008 18:59:17 -0700 Subject: x86: fix APIC_DEBUG with inquire_remote_apic APIC_DEBUG is always 2. need to update inquire_remote_apic to check apic_verbosity with it instead. Signed-off-by: Yinghai Lu Signed-off-by: Ingo Molnar --- arch/x86/include/asm/es7000/wakecpu.h | 9 ++++----- arch/x86/include/asm/mach-default/mach_wakecpu.h | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/es7000/wakecpu.h b/arch/x86/include/asm/es7000/wakecpu.h index 3ffc5a7bf66..39849346191 100644 --- a/arch/x86/include/asm/es7000/wakecpu.h +++ b/arch/x86/include/asm/es7000/wakecpu.h @@ -50,10 +50,9 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { } -#if APIC_DEBUG - #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid) -#else - #define inquire_remote_apic(apicid) {} -#endif +#define inquire_remote_apic(apicid) do { \ + if (apic_verbosity >= APIC_DEBUG) \ + __inquire_remote_apic(apicid); \ + } while (0) #endif /* __ASM_MACH_WAKECPU_H */ diff --git a/arch/x86/include/asm/mach-default/mach_wakecpu.h b/arch/x86/include/asm/mach-default/mach_wakecpu.h index d5c0b826a4f..9d80db91e99 100644 --- a/arch/x86/include/asm/mach-default/mach_wakecpu.h +++ b/arch/x86/include/asm/mach-default/mach_wakecpu.h @@ -33,10 +33,9 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { } -#if APIC_DEBUG - #define inquire_remote_apic(apicid) __inquire_remote_apic(apicid) -#else - #define inquire_remote_apic(apicid) {} -#endif +#define inquire_remote_apic(apicid) do { \ + if (apic_verbosity >= APIC_DEBUG) \ + __inquire_remote_apic(apicid); \ + } while (0) #endif /* _ASM_X86_MACH_DEFAULT_MACH_WAKECPU_H */ -- cgit v1.2.3 From e7706fc691513b0f06adb3de3d6ac04293180146 Mon Sep 17 00:00:00 2001 From: Ken'ichi Ohmichi Date: Mon, 20 Oct 2008 13:51:52 +0900 Subject: x86, kdump: fix invalid access on i386 sparsemem Impact: fix kdump crash on 32-bit sparsemem kernels Since linux-2.6.27, kdump has failed on i386 sparsemem kernel. 1st-kernel gets a panic just before switching to 2nd-kernel. The cause is that a kernel accesses invalid mem_section by page_to_pfn(image->swap_page) at machine_kexec(). image->swap_page is allocated if kexec for hibernation, but it is not allocated if kdump. So if kdump, a kernel should not access the mem_section corresponding to image->swap_page. The attached patch fixes this invalid access. Signed-off-by: Ken'ichi Ohmichi Cc: kexec-ml Cc: Andrew Morton Signed-off-by: Ingo Molnar --- arch/x86/kernel/machine_kexec_32.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c index 0732adba05c..7a385746509 100644 --- a/arch/x86/kernel/machine_kexec_32.c +++ b/arch/x86/kernel/machine_kexec_32.c @@ -162,7 +162,10 @@ void machine_kexec(struct kimage *image) page_list[VA_PTE_0] = (unsigned long)kexec_pte0; page_list[PA_PTE_1] = __pa(kexec_pte1); page_list[VA_PTE_1] = (unsigned long)kexec_pte1; - page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) << PAGE_SHIFT); + + if (image->type == KEXEC_TYPE_DEFAULT) + page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) + << PAGE_SHIFT); /* The segment registers are funny things, they have both a * visible and an invisible part. Whenever the visible part is -- cgit v1.2.3 From 11a6b0c933b55654a58afd84f63a5dde1607d78f Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Tue, 14 Oct 2008 18:59:18 -0700 Subject: x86: 64 bit print out absent pages num too so users are not confused with memhole causing big total ram we don't need to worry about 32 bit, because memhole is always above max_low_pfn. Signed-off-by: Yinghai Lu Signed-off-by: Ingo Molnar --- arch/x86/mm/init_64.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index f79a02f64d1..ad38648bddb 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -884,6 +884,7 @@ static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, void __init mem_init(void) { long codesize, reservedpages, datasize, initsize; + unsigned long absent_pages; start_periodic_check_for_corruption(); @@ -899,8 +900,9 @@ void __init mem_init(void) #else totalram_pages = free_all_bootmem(); #endif - reservedpages = max_pfn - totalram_pages - - absent_pages_in_range(0, max_pfn); + + absent_pages = absent_pages_in_range(0, max_pfn); + reservedpages = max_pfn - totalram_pages - absent_pages; after_bootmem = 1; codesize = (unsigned long) &_etext - (unsigned long) &_text; @@ -917,10 +919,11 @@ void __init mem_init(void) VSYSCALL_END - VSYSCALL_START); printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " - "%ldk reserved, %ldk data, %ldk init)\n", + "%ldk absent, %ldk reserved, %ldk data, %ldk init)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), max_pfn << (PAGE_SHIFT-10), codesize >> 10, + absent_pages << (PAGE_SHIFT-10), reservedpages << (PAGE_SHIFT-10), datasize >> 10, initsize >> 10); -- cgit v1.2.3 From 87c6f40128f92621698f97a62d2ead5184d1dd97 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Tue, 28 Oct 2008 16:13:54 +0100 Subject: x86, gart: fix gart detection for Fam11h CPUs Impact: fix AMD Family 11h boot hangs / USB device problems The AMD Fam11h CPUs have a K8 northbridge. This northbridge is different from other family's because it lacks GART support (as I just learned). But the kernel implicitly expects a GART if it finds an AMD northbridge. Fix this by removing the Fam11h northbridge id from the scan list of K8 northbridges. This patch also changes the message in the GART driver about missing K8 northbridges to tell that the GART is missing which is the correct information in this case. Reported-by: Jouni Malinen Signed-off-by: Joerg Roedel Signed-off-by: Ingo Molnar --- arch/x86/kernel/k8.c | 1 - arch/x86/kernel/pci-gart_64.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/k8.c b/arch/x86/kernel/k8.c index 304d8bad655..cbc4332a77b 100644 --- a/arch/x86/kernel/k8.c +++ b/arch/x86/kernel/k8.c @@ -18,7 +18,6 @@ static u32 *flush_words; struct pci_device_id k8_nb_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, {} }; EXPORT_SYMBOL(k8_nb_ids); diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c index e3f75bbcede..a42b02b4df6 100644 --- a/arch/x86/kernel/pci-gart_64.c +++ b/arch/x86/kernel/pci-gart_64.c @@ -744,7 +744,7 @@ void __init gart_iommu_init(void) long i; if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) { - printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n"); + printk(KERN_INFO "PCI-GART: No AMD GART found.\n"); return; } -- cgit v1.2.3 From f96f57d91c2df75011d1e260c23edca429f37361 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Tue, 28 Oct 2008 12:39:23 -0700 Subject: x86: fix init_memory_mapping for [dc000000 - e0000000) - v2 Impact: change over-mapping to precise mapping, fix /proc/meminfo output v2: fix less than 1G ram system handling when gart aperture is 0xdc000000 - 0xe0000000 it return 0xc0000000 - 0xe0000000 that is not right. this patch fix that will get exact mapping on 256g sytem with that aperture after patch LBSuse:~ # cat /proc/meminfo MemTotal: 264742432 kB MemFree: 263920628 kB Buffers: 1416 kB Cached: 24468 kB ... DirectMap4k: 5760 kB DirectMap2M: 3205120 kB DirectMap1G: 265289728 kB it is consistent to LBSuse:~ # cat /sys/kernel/debug/kernel_page_tables .. ---[ Low Kernel Mapping ]--- 0xffff880000000000-0xffff880000200000 2M RW GLB x pte 0xffff880000200000-0xffff880040000000 1022M RW PSE GLB x pmd 0xffff880040000000-0xffff8800c0000000 2G RW PSE GLB NX pud 0xffff8800c0000000-0xffff8800d7e00000 382M RW PSE GLB NX pmd 0xffff8800d7e00000-0xffff8800d7fa0000 1664K RW GLB NX pte 0xffff8800d7fa0000-0xffff8800d8000000 384K pte 0xffff8800d8000000-0xffff8800dc000000 64M pmd 0xffff8800dc000000-0xffff8800e0000000 64M RW PSE GLB NX pmd 0xffff8800e0000000-0xffff880100000000 512M pmd 0xffff880100000000-0xffff880800000000 28G RW PSE GLB NX pud 0xffff880800000000-0xffff880824600000 582M RW PSE GLB NX pmd 0xffff880824600000-0xffff8808247f0000 1984K RW GLB NX pte 0xffff8808247f0000-0xffff880824800000 64K RW PCD GLB NX pte 0xffff880824800000-0xffff880840000000 440M RW PSE GLB NX pmd 0xffff880840000000-0xffff884000000000 223G RW PSE GLB NX pud 0xffff884000000000-0xffff884028000000 640M RW PSE GLB NX pmd 0xffff884028000000-0xffff884040000000 384M pmd 0xffff884040000000-0xffff888000000000 255G pud 0xffff888000000000-0xffffc20000000000 58880G pgd Signed-off-by: Yinghai Lu Signed-off-by: Ingo Molnar --- arch/x86/mm/init_64.c | 50 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index ad38648bddb..ebe1811e5b1 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -671,12 +671,13 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, unsigned long last_map_addr = 0; unsigned long page_size_mask = 0; unsigned long start_pfn, end_pfn; + unsigned long pos; struct map_range mr[NR_RANGE_MR]; int nr_range, i; int use_pse, use_gbpages; - printk(KERN_INFO "init_memory_mapping\n"); + printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end); /* * Find space for the kernel direct mapping tables. @@ -710,35 +711,50 @@ unsigned long __init_refok init_memory_mapping(unsigned long start, /* head if not big page alignment ?*/ start_pfn = start >> PAGE_SHIFT; - end_pfn = ((start + (PMD_SIZE - 1)) >> PMD_SHIFT) + pos = start_pfn << PAGE_SHIFT; + end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); + pos = end_pfn << PAGE_SHIFT; + } /* big page (2M) range*/ - start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT) + start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - end_pfn = ((start + (PUD_SIZE - 1))>>PUD_SHIFT) + end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); - if (end_pfn > ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT))) - end_pfn = ((end>>PUD_SHIFT)<<(PUD_SHIFT - PAGE_SHIFT)); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, - page_size_mask & (1< ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT))) + end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + page_size_mask & (1<>PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) + << (PUD_SHIFT - PAGE_SHIFT); + end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, page_size_mask & ((1<>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); - nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, - page_size_mask & (1<>PMD_SHIFT) + << (PMD_SHIFT - PAGE_SHIFT); + end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); + if (start_pfn < end_pfn) { + nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, + page_size_mask & (1<>PAGE_SHIFT; end_pfn = end>>PAGE_SHIFT; nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); -- cgit v1.2.3 From b6e642e498097e3d66e25ee9499f7719976263cf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov <[dbaryshkov@gmail.com]> Date: Wed, 29 Oct 2008 11:40:46 +0800 Subject: [ARM] pxa/spitz: fix spi cs on spitz On spitz configure SPI CS GPIOs as outputs to unbreak spi chip selection. Signed-off-by: Dmitry Baryshkov Signed-off-by: Eric Miao --- arch/arm/mach-pxa/spitz.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 524f656dc56..f0a5bbae0b4 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -385,6 +385,16 @@ static void __init spitz_init_spi(void) if (err) goto err_free_2; + err = gpio_direction_output(SPITZ_GPIO_ADS7846_CS, 1); + if (err) + goto err_free_3; + err = gpio_direction_output(SPITZ_GPIO_LCDCON_CS, 1); + if (err) + goto err_free_3; + err = gpio_direction_output(SPITZ_GPIO_MAX1111_CS, 1); + if (err) + goto err_free_3; + if (machine_is_akita()) { spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; @@ -394,6 +404,8 @@ static void __init spitz_init_spi(void) spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices)); return; +err_free_3: + gpio_free(SPITZ_GPIO_MAX1111_CS); err_free_2: gpio_free(SPITZ_GPIO_LCDCON_CS); err_free_1: -- cgit v1.2.3 From 5cbff9603a77d01315859690a8f125f817bed73b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2008 20:26:40 +0300 Subject: [ARM] corgi_lcd: fix simultaneous compilation with corgi_bl corgi_lcd has symbol conflict with corgi_bl driver. Fix it by renaming common symbol in new corgi_lcd driver. Signed-off-by: Dmitry Baryshkov Signed-off-by: Eric Miao --- arch/arm/mach-pxa/corgi_pm.c | 4 +++- arch/arm/mach-pxa/include/mach/sharpsl.h | 1 + arch/arm/mach-pxa/spitz_pm.c | 4 +++- 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index eb7d6c94aa4..e3525903281 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -204,7 +204,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { .read_devdata = corgipm_read_devdata, .charger_wakeup = corgi_charger_wakeup, .should_wakeup = corgi_should_wakeup, -#ifdef CONFIG_BACKLIGHT_CORGI +#if defined(CONFIG_LCD_CORGI) + .backlight_limit = corgi_lcd_limit_intensity, +#elif defined(CONFIG_BACKLIGHT_CORGI) .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, diff --git a/arch/arm/mach-pxa/include/mach/sharpsl.h b/arch/arm/mach-pxa/include/mach/sharpsl.h index 3b1d4a72d4d..8242e14a44f 100644 --- a/arch/arm/mach-pxa/include/mach/sharpsl.h +++ b/arch/arm/mach-pxa/include/mach/sharpsl.h @@ -26,6 +26,7 @@ struct corgits_machinfo { * SharpSL Backlight */ extern void corgibl_limit_intensity(int limit); +extern void corgi_lcd_limit_intensity(int limit); /* diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 53018db106a..072e77cfe5a 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -198,7 +198,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { .read_devdata = spitzpm_read_devdata, .charger_wakeup = spitz_charger_wakeup, .should_wakeup = spitz_should_wakeup, -#ifdef CONFIG_BACKLIGHT_CORGI +#if defined(CONFIG_LCD_CORGI) + .backlight_limit = corgi_lcd_limit_intensity, +#elif defined(CONFIG_BACKLIGHT_CORGI) .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, -- cgit v1.2.3 From 9352f5698db2c6d7f2789f6cd37e3996d49ac4b5 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Tue, 28 Oct 2008 23:05:22 -0700 Subject: x86: two trivial sparse annotations Impact: fewer sparse warnings, no functional changes arch/x86/kernel/vsmp_64.c:87:14: warning: incorrect type in argument 1 (different address spaces) arch/x86/kernel/vsmp_64.c:87:14: expected void const volatile [noderef] *addr arch/x86/kernel/vsmp_64.c:87:14: got void *[assigned] address arch/x86/kernel/vsmp_64.c:88:22: warning: incorrect type in argument 1 (different address spaces) arch/x86/kernel/vsmp_64.c:88:22: expected void const volatile [noderef] *addr arch/x86/kernel/vsmp_64.c:88:22: got void * arch/x86/kernel/vsmp_64.c:100:23: warning: incorrect type in argument 2 (different address spaces) arch/x86/kernel/vsmp_64.c:100:23: expected void volatile [noderef] *addr arch/x86/kernel/vsmp_64.c:100:23: got void * arch/x86/kernel/vsmp_64.c:101:23: warning: incorrect type in argument 1 (different address spaces) arch/x86/kernel/vsmp_64.c:101:23: expected void const volatile [noderef] *addr arch/x86/kernel/vsmp_64.c:101:23: got void * arch/x86/mm/gup.c:235:6: warning: incorrect type in argument 1 (different base types) arch/x86/mm/gup.c:235:6: expected void const volatile [noderef] * arch/x86/mm/gup.c:235:6: got unsigned long [unsigned] [assigned] start Signed-off-by: Harvey Harrison Signed-off-by: Ingo Molnar --- arch/x86/kernel/vsmp_64.c | 2 +- arch/x86/mm/gup.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c index 7766d36983f..a688f3bfaec 100644 --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -78,7 +78,7 @@ static unsigned __init_or_module vsmp_patch(u8 type, u16 clobbers, void *ibuf, static void __init set_vsmp_pv_ops(void) { - void *address; + void __iomem *address; unsigned int cap, ctl, cfg; /* set vSMP magic bits to indicate vSMP capable kernel */ diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 4ba373c5b8c..be54176e9eb 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -233,7 +233,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, len = (unsigned long) nr_pages << PAGE_SHIFT; end = start + len; if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ, - start, len))) + (void __user *)start, len))) goto slow_irqon; /* -- cgit v1.2.3 From 1d6cf1feb854c53c6d59e0d879603692b379e208 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Tue, 28 Oct 2008 22:46:04 -0700 Subject: x86: start annotating early ioremap pointers with __iomem Impact: some new sparse warnings in e820.c etc, but no functional change. As with regular ioremap, iounmap etc, annotate with __iomem. Fixes the following sparse warnings, will produce some new ones elsewhere in arch/x86 that will get worked out over time. arch/x86/mm/ioremap.c:402:9: warning: cast removes address space of expression arch/x86/mm/ioremap.c:406:10: warning: cast adds address space to expression () arch/x86/mm/ioremap.c:782:19: warning: Using plain integer as NULL pointer Signed-off-by: Harvey Harrison Signed-off-by: Ingo Molnar --- arch/x86/include/asm/io.h | 6 +++--- arch/x86/mm/ioremap.c | 22 +++++++++++----------- 2 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 5618a103f39..ac2abc88cd9 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -82,9 +82,9 @@ extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size); extern void early_ioremap_init(void); extern void early_ioremap_clear(void); extern void early_ioremap_reset(void); -extern void *early_ioremap(unsigned long offset, unsigned long size); -extern void *early_memremap(unsigned long offset, unsigned long size); -extern void early_iounmap(void *addr, unsigned long size); +extern void __iomem *early_ioremap(unsigned long offset, unsigned long size); +extern void __iomem *early_memremap(unsigned long offset, unsigned long size); +extern void early_iounmap(void __iomem *addr, unsigned long size); extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index ae71e11eb3e..d4c4307ff3e 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -387,7 +387,7 @@ static void __iomem *ioremap_default(resource_size_t phys_addr, unsigned long size) { unsigned long flags; - void *ret; + void __iomem *ret; int err; /* @@ -399,11 +399,11 @@ static void __iomem *ioremap_default(resource_size_t phys_addr, if (err < 0) return NULL; - ret = (void *) __ioremap_caller(phys_addr, size, flags, - __builtin_return_address(0)); + ret = __ioremap_caller(phys_addr, size, flags, + __builtin_return_address(0)); free_memtype(phys_addr, phys_addr + size); - return (void __iomem *)ret; + return ret; } void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size, @@ -622,7 +622,7 @@ static inline void __init early_clear_fixmap(enum fixed_addresses idx) __early_set_fixmap(idx, 0, __pgprot(0)); } -static void *prev_map[FIX_BTMAPS_SLOTS] __initdata; +static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata; static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata; static int __init check_early_ioremap_leak(void) { @@ -645,7 +645,7 @@ static int __init check_early_ioremap_leak(void) } late_initcall(check_early_ioremap_leak); -static void __init *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) +static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) { unsigned long offset, last_addr; unsigned int nrpages; @@ -713,23 +713,23 @@ static void __init *__early_ioremap(unsigned long phys_addr, unsigned long size, if (early_ioremap_debug) printk(KERN_CONT "%08lx + %08lx\n", offset, fix_to_virt(idx0)); - prev_map[slot] = (void *) (offset + fix_to_virt(idx0)); + prev_map[slot] = (void __iomem *)(offset + fix_to_virt(idx0)); return prev_map[slot]; } /* Remap an IO device */ -void __init *early_ioremap(unsigned long phys_addr, unsigned long size) +void __init __iomem *early_ioremap(unsigned long phys_addr, unsigned long size) { return __early_ioremap(phys_addr, size, PAGE_KERNEL_IO); } /* Remap memory */ -void __init *early_memremap(unsigned long phys_addr, unsigned long size) +void __init __iomem *early_memremap(unsigned long phys_addr, unsigned long size) { return __early_ioremap(phys_addr, size, PAGE_KERNEL); } -void __init early_iounmap(void *addr, unsigned long size) +void __init early_iounmap(void __iomem *addr, unsigned long size) { unsigned long virt_addr; unsigned long offset; @@ -779,7 +779,7 @@ void __init early_iounmap(void *addr, unsigned long size) --idx; --nrpages; } - prev_map[slot] = 0; + prev_map[slot] = NULL; } void __this_fixmap_does_not_exist(void) -- cgit v1.2.3 From fe8b868eccb9f85a0e231e35f0abac5b39bac801 Mon Sep 17 00:00:00 2001 From: Gary Hade Date: Tue, 28 Oct 2008 16:43:14 -0700 Subject: x86: remove debug code from arch_add_memory() Impact: remove incorrect WARN_ON(1) Gets rid of dmesg spam created during physical memory hot-add which will very likely confuse users. The change removes what appears to be debugging code which I assume was unintentionally included in: x86: arch/x86/mm/init_64.c printk fixes commit 10f22dde556d1ed41d55355d1fb8ad495f9810c8 Signed-off-by: Gary Hade Signed-off-by: Ingo Molnar --- arch/x86/mm/init_64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index ebe1811e5b1..9db01db6e3c 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -858,7 +858,7 @@ int arch_add_memory(int nid, u64 start, u64 size) max_pfn_mapped = last_mapped_pfn; ret = __add_pages(zone, start_pfn, nr_pages); - WARN_ON(1); + WARN_ON_ONCE(ret); return ret; } -- cgit v1.2.3 From 6c1249e588cbf0484fc3e6b0f0fc4a5892749b4d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 18 Sep 2008 15:48:23 +0200 Subject: [ARM] pcm037: map AIPS1 and AIPS2 as nonshared area The internal devices of the MX3 Processor have to be mapped MT_DEVICE_NONSHARED devices, otherwise cache corruptions occur. Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/pcm037.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 11fda95c86a..843f68c8ead 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c @@ -91,12 +91,12 @@ static struct map_desc pcm037_io_desc[] __initdata = { .virtual = AIPS1_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), .length = AIPS1_SIZE, - .type = MT_DEVICE + .type = MT_DEVICE_NONSHARED }, { .virtual = AIPS2_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), .length = AIPS2_SIZE, - .type = MT_DEVICE + .type = MT_DEVICE_NONSHARED }, }; -- cgit v1.2.3 From ab00fee30cddf975200b3c97aef25bea144a0d89 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 30 Oct 2008 10:37:21 +0000 Subject: i386/PAE: fix pud_page() Impact: cleanup To the unsuspecting user it is quite annoying that this broken and inconsistent with x86-64 definition still exists. Signed-off-by: Jan Beulich Signed-off-by: Ingo Molnar --- arch/x86/include/asm/pgtable-3level.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index fb16cec702e..52597aeadff 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -120,13 +120,13 @@ static inline void pud_clear(pud_t *pudp) write_cr3(pgd); } -#define pud_page(pud) ((struct page *) __va(pud_val(pud) & PTE_PFN_MASK)) +#define pud_page(pud) pfn_to_page(pud_val(pud) >> PAGE_SHIFT) #define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PTE_PFN_MASK)) /* Find an entry in the second-level page table.. */ -#define pmd_offset(pud, address) ((pmd_t *)pud_page(*(pud)) + \ +#define pmd_offset(pud, address) ((pmd_t *)pud_page_vaddr(*(pud)) + \ pmd_index(address)) #ifdef CONFIG_SMP -- cgit v1.2.3 From 56e7d85cf982dda4b453c157f3f64aea1478bc4d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 17 Oct 2008 02:34:41 +0400 Subject: [ARM] sharpsl_pm: fix compilation w/o CONFIG_PM Fix compilation of sharpsl_pm when CONFIG_PM in unselected. Signed-off-by: Dmitry Baryshkov Acked-by: Russell King Signed-off-by: Eric Miao --- arch/arm/common/sharpsl_pm.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index db830916140..780bbf7cb26 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c @@ -54,11 +54,13 @@ /* * Prototypes */ +#ifdef CONFIG_PM static int sharpsl_off_charge_battery(void); -static int sharpsl_check_battery_temp(void); static int sharpsl_check_battery_voltage(void); -static int sharpsl_ac_check(void); static int sharpsl_fatal_check(void); +#endif +static int sharpsl_check_battery_temp(void); +static int sharpsl_ac_check(void); static int sharpsl_average_value(int ad); static void sharpsl_average_clear(void); static void sharpsl_charge_toggle(struct work_struct *private_); @@ -424,6 +426,7 @@ static int sharpsl_check_battery_temp(void) return 0; } +#ifdef CONFIG_PM static int sharpsl_check_battery_voltage(void) { int val, i, buff[5]; @@ -455,6 +458,7 @@ static int sharpsl_check_battery_voltage(void) return 0; } +#endif static int sharpsl_ac_check(void) { @@ -586,8 +590,6 @@ static int corgi_pxa_pm_enter(suspend_state_t state) return 0; } -#endif - /* * Check for fatal battery errors @@ -738,7 +740,10 @@ static int sharpsl_off_charge_battery(void) } } } - +#else +#define sharpsl_pm_suspend NULL +#define sharpsl_pm_resume NULL +#endif static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -768,10 +773,12 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info) info->battery_life = sharpsl_pm.battstat.mainbat_percent; } +#ifdef CONFIG_PM static struct platform_suspend_ops sharpsl_pm_ops = { .enter = corgi_pxa_pm_enter, .valid = suspend_valid_only_mem, }; +#endif static int __init sharpsl_pm_probe(struct platform_device *pdev) { @@ -802,7 +809,9 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) apm_get_power_status = sharpsl_apm_get_power_status; +#ifdef CONFIG_PM suspend_set_ops(&sharpsl_pm_ops); +#endif mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250)); -- cgit v1.2.3 From 63890a0ee1af994122094bd01f87ea6251631a3f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 29 Oct 2008 14:14:52 -0700 Subject: [ARM] ep93xx: fix OHCI DMA mask Signed-off-by: Matthias Kaehlcke Signed-off-by: Andrew Morton Signed-off-by: Russell King --- arch/arm/mach-ep93xx/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index de53f0be71b..48345fb3461 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -449,12 +450,13 @@ static struct resource ep93xx_ohci_resources[] = { }, }; + static struct platform_device ep93xx_ohci_device = { .name = "ep93xx-ohci", .id = -1, .dev = { - .dma_mask = (void *)0xffffffff, - .coherent_dma_mask = 0xffffffff, + .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), .resource = ep93xx_ohci_resources, -- cgit v1.2.3 From 9c6568501cbf731a910db2fcb7d094977dcb154c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 29 Oct 2008 14:14:54 -0700 Subject: [ARM] gpio_free might sleep, arm architecture MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the documentation gpio_free should only be called from task context only. To make this more explicit add a might sleep to all implementations. This patch changes the gpio_free implementations for the arm architecture. DaVinci is skipped on purpose to simplify the merge process for patches switching it over to use gpiolib as per request by David Brownell. Signed-off-by: Uwe Kleine-König Cc: David Brownell Cc: Andrew Victor Signed-off-by: Andrew Morton Signed-off-by: Russell King --- arch/arm/mach-at91/include/mach/gpio.h | 2 ++ arch/arm/mach-imx/include/mach/gpio.h | 3 +++ arch/arm/mach-ixp4xx/include/mach/gpio.h | 3 +++ arch/arm/mach-ks8695/include/mach/gpio.h | 3 +++ arch/arm/mach-ns9xxx/gpio.c | 2 ++ arch/arm/mach-orion5x/gpio.c | 2 ++ 6 files changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 76d76e2fa69..bffa6741a75 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARCH_AT91RM9200_GPIO_H #define __ASM_ARCH_AT91RM9200_GPIO_H +#include #include #define PIN_BASE NR_AIC_IRQS @@ -220,6 +221,7 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); } extern int gpio_direction_input(unsigned gpio); diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h index 6e3d795f226..502d5aa2c09 100644 --- a/arch/arm/mach-imx/include/mach/gpio.h +++ b/arch/arm/mach-imx/include/mach/gpio.h @@ -1,5 +1,6 @@ #ifndef _IMX_GPIO_H +#include #include #define IMX_GPIO_ALLOC_MODE_NORMAL 0 @@ -63,6 +64,8 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); + imx_gpio_free(gpio); } diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h index 9fbde177920..cd5aec26c07 100644 --- a/arch/arm/mach-ixp4xx/include/mach/gpio.h +++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h @@ -25,6 +25,7 @@ #ifndef __ASM_ARCH_IXP4XX_GPIO_H #define __ASM_ARCH_IXP4XX_GPIO_H +#include #include static inline int gpio_request(unsigned gpio, const char *label) @@ -34,6 +35,8 @@ static inline int gpio_request(unsigned gpio, const char *label) static inline void gpio_free(unsigned gpio) { + might_sleep(); + return; } diff --git a/arch/arm/mach-ks8695/include/mach/gpio.h b/arch/arm/mach-ks8695/include/mach/gpio.h index 73c84168761..d4af5c335f1 100644 --- a/arch/arm/mach-ks8695/include/mach/gpio.h +++ b/arch/arm/mach-ks8695/include/mach/gpio.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_GPIO_H_ #define __ASM_ARCH_GPIO_H_ +#include + #define KS8695_GPIO_0 0 #define KS8695_GPIO_1 1 #define KS8695_GPIO_2 2 @@ -74,6 +76,7 @@ static inline int gpio_request(unsigned int pin, const char *label) static inline void gpio_free(unsigned int pin) { + might_sleep(); } #endif diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c index 5241e6a286c..5503ca09c4a 100644 --- a/arch/arm/mach-ns9xxx/gpio.c +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -8,6 +8,7 @@ * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ +#include #include #include #include @@ -63,6 +64,7 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { + might_sleep(); clear_bit(gpio, gpiores); return; } diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c index fc419868e39..f99d08811e5 100644 --- a/arch/arm/mach-orion5x/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -165,6 +165,8 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned pin) { + might_sleep(); + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { pr_debug("%s: invalid GPIO %d\n", __func__, pin); return; -- cgit v1.2.3 From 9cc4581528233e2a4eb8720621c1e2f613d7c38a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 11 Sep 2008 00:44:04 +0900 Subject: MIPS: TXx9: Fix RBTX4939 ethernet address initialization Fix location of ethernet adddress when booted from external ROM. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/rbtx4939/setup.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 6daee9b1cd5..98fbd9391bf 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -308,16 +308,22 @@ static void __init rbtx4939_device_init(void) #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) int i, j; unsigned char ethaddr[2][6]; + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + for (i = 0; i < 2; i++) { unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); - if (readb(rbtx4939_bdipsw_addr) & 8) { + if (bdipsw == 0) + memcpy(ethaddr[i], (void *)area, 6); + else { u16 buf[3]; - area -= 0x03000000; + if (bdipsw & 8) + area -= 0x03000000; + else + area -= 0x01000000; for (j = 0; j < 3; j++) buf[j] = le16_to_cpup((u16 *)(area + j * 2)); memcpy(ethaddr[i], buf, 6); - } else - memcpy(ethaddr[i], (void *)area, 6); + } } tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); #endif -- cgit v1.2.3 From 864cbf804ddfb3d63d3ba3cca7afdeb98be23434 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 2 Sep 2008 22:44:38 +0900 Subject: MIPS: RBTX4927: Add GPIO-LED support Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/rbtx4927/setup.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 4a74423b2ba..01129a9d50f 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void) /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); - gpio_request(0, "led"); - gpio_direction_output(0, 1); - gpio_request(1, "led"); - gpio_direction_output(1, 1); tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE @@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void) tx4927_mtd_init(i); } +static void __init rbtx4927_gpioled_init(void) +{ + static struct gpio_led leds[] = { + { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, + { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, + }; + static struct gpio_led_platform_data pdata = { + .num_leds = ARRAY_SIZE(leds), + .leds = leds, + }; + struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); + + if (!pdev) + return; + pdev->dev.platform_data = &pdata; + if (platform_device_add(pdev)) + platform_device_put(pdev); +} + static void __init rbtx4927_device_init(void) { toshiba_rbtx4927_rtc_init(); @@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void) tx4927_wdt_init(); rbtx4927_mtd_init(); txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); + rbtx4927_gpioled_init(); } struct txx9_board_vec rbtx4927_vec __initdata = { -- cgit v1.2.3 From c46b302b948e2070cb713171207c42e9586f131a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 09:37:47 +0000 Subject: MIPS: New feature test macro cpu_has_mips_r cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture revision. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 5ea701fc342..12d12dfe73c 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -141,6 +141,8 @@ #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ + cpu_has_mips64r1 | cpu_has_mips64r2) #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) -- cgit v1.2.3 From 4816227b54d2366cba785e6f3b9f81495b83a5f1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 09:40:35 +0000 Subject: MIPS: Clean up MIPSxx-optimized bitop functions Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bitops.h | 114 +++++++++++++++++++++++++++-------------- 1 file changed, 76 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 49df8c4c9d2..bac4a960b24 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * __clear_bit(nr, addr); } -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static inline unsigned long __fls(unsigned long x) +static inline unsigned long __fls(unsigned long word) { - int lz; + int num; - if (sizeof(x) == 4) { + if (BITS_PER_LONG == 32 && + __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" - : "=r" (lz) - : "r" (x)); + : "=r" (num) + : "r" (word)); - return 31 - lz; + return 31 - num; } - BUG_ON(sizeof(x) != 8); + if (BITS_PER_LONG == 64 && + __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { + __asm__( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (num) + : "r" (word)); - __asm__( - " .set push \n" - " .set mips64 \n" - " dclz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); + return 63 - num; + } + + num = BITS_PER_LONG - 1; - return 63 - lz; +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; } /* @@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word) * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ -static inline int fls(int word) +static inline int fls(int x) { - __asm__("clz %0, %1" : "=r" (word) : "r" (word)); + int r; - return 32 - word; -} + if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __asm__("clz %0, %1" : "=r" (x) : "r" (x)); -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) -static inline int fls64(__u64 word) -{ - __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); + return 32 - x; + } - return 64 - word; + r = 32; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; } -#else + #include -#endif /* * ffs - find first bit set. @@ -646,16 +694,6 @@ static inline int ffs(int word) return fls(word & -word); } -#else - -#include -#include -#include -#include -#include - -#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ - #include #include -- cgit v1.2.3 From 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 23 Oct 2008 17:56:35 -0700 Subject: MIPS: Consider value of c0_ebase when computing value of exception base. It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 80b9e070c20..3f6de76d485 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1555,6 +1555,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1588,8 +1590,11 @@ void __init trap_init(void) if (cpu_has_veic || cpu_has_vint) ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else + else { ebase = CAC_BASE; + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); + } per_cpu_trap_init(); @@ -1697,11 +1702,11 @@ void __init trap_init(void) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); signal_init(); #ifdef CONFIG_MIPS32_COMPAT -- cgit v1.2.3 From 076c6e4f4d81113615f50e5bc2c569f628bcd54a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 10:03:57 +0000 Subject: MIPS: SMP: Do not initialize __cpu_number_map/__cpu_logical_map for CPU 0. A system isn't necessarily booted on physical processor 0 as this code assumes. Also the array happens to be allocated in .bss so it's zero initialized anyway. Systems which need to override this can do so in their mp_ops->smp_setup() method. Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index b79ea7055ec..8bf88faf5af 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -195,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) /* preload SMP state for boot cpu */ void __devinit smp_prepare_boot_cpu(void) { - /* - * This assumes that bootup is always handled by the processor - * with the logic and physical number 0. - */ - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; cpu_set(0, phys_cpu_present_map); cpu_set(0, cpu_online_map); cpu_set(0, cpu_callin_map); -- cgit v1.2.3 From ba3049ed4086737dab200b6087138a4b8e06915d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 17:38:42 +0000 Subject: MIPS: Switch FPU emulator trap to BREAK instruction. Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/break.h | 1 + arch/mips/include/asm/fpu_emulator.h | 17 +++++++++++++++++ arch/mips/kernel/traps.c | 16 ++++++++++++++++ arch/mips/kernel/unaligned.c | 12 ------------ arch/mips/math-emu/cp1emu.c | 4 ---- arch/mips/math-emu/dsemul.c | 7 +++---- arch/mips/math-emu/dsemul.h | 17 ----------------- 7 files changed, 37 insertions(+), 37 deletions(-) delete mode 100644 arch/mips/math-emu/dsemul.h (limited to 'arch') diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 25b980c91e7..44437ed765e 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -29,6 +29,7 @@ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 2731c38bd7a..e5189572956 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -23,6 +23,9 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H +#include +#include + struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; @@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats { extern struct mips_fpu_emulator_stats fpuemustats; +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); + +/* + * Instruction inserted following the badinst to further tag the sequence + */ +#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ + +/* + * Break instruction with special math emu break code set + */ +#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 3f6de76d485..353056110f2 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, die_if_kernel("Kernel bug detected", regs); force_sig(SIGTRAP, current); break; + case BRK_MEMU: + /* + * Address errors may be deliberately induced by the FPU + * emulator to retake control of the CPU after executing the + * instruction in the delay slot of an emulated branch. + * + * Terminate if exception was recognized as a delay slot return + * otherwise handle as normal. + */ + if (do_dsemulret(regs)) + return; + + die_if_kernel("Math emu break/trap", regs); + force_sig(SIGTRAP, current); + break; default: scnprintf(b, sizeof(b), "%s instruction in kernel code", str); die_if_kernel(b, regs); diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 20709669e59..bf4c4a979ab 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -499,21 +499,9 @@ sigill: asmlinkage void do_ade(struct pt_regs *regs) { - extern int do_dsemulret(struct pt_regs *); unsigned int __user *pc; mm_segment_t seg; - /* - * Address errors may be deliberately induced by the FPU emulator to - * retake control of the CPU after executing the instruction in the - * delay slot of an emulated branch. - */ - /* Terminate if exception was recognized as a delay slot return */ - if (do_dsemulret(regs)) - return; - - /* Otherwise handle as normal */ - /* * Did we catch a fault trying to load an instruction? * Or are we running in MIPS16 mode? diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 7ec0b217dfd..890f77927d6 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -48,7 +48,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) /* cop control register rd -> gpr[rt] */ u32 value; - if (ir == CP1UNDEF) { - return do_dsemulret(xcp); - } if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; value = (value & ~0x3) | mips_rm[value & 0x3]; diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 653e325849e..df7b9d928ef 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -18,7 +18,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BADINST, &fr->badinst); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp) /* * Do some sanity checking on the stackframe: * - * - Is the instruction pointed to by the EPC an BADINST? + * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { fpuemustats.errors++; return 0; } diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h deleted file mode 100644 index 091f0e76730..00000000000 --- a/arch/mips/math-emu/dsemul.h +++ /dev/null @@ -1,17 +0,0 @@ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); -extern int do_dsemulret(struct pt_regs *xcp); - -/* Instruction which will always cause an address error */ -#define AdELOAD 0x8c000001 /* lw $0,1($0) */ -/* Instruction which will plainly cause a CP1 exception when FPU is disabled */ -#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */ - -/* Instruction inserted following the badinst to further tag the sequence */ -#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */ - -/* Setup which instruction to use for trampoline */ -#ifdef STANDALONE_EMULATOR -#define BADINST CP1UNDEF -#else -#define BADINST AdELOAD -#endif -- cgit v1.2.3 From 558ce12494e9e0321b77b9f1ef62c16d0b893cf5 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 29 Oct 2008 12:33:34 +0000 Subject: MIPS: Probe for watch registers on cores of all vendors, not just MTI. Signed-off-by: Ralf Baechle Acked-by: David Daney --- arch/mips/kernel/cpu-probe.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0cf15457eca..41a1d07b475 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -652,21 +652,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) static void __cpuinit decode_configs(struct cpuinfo_mips *c) { + int ok; + /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; - /* Read Config registers. */ - if (!decode_config0(c)) - return; /* actually worth a panic() */ - if (!decode_config1(c)) - return; - if (!decode_config2(c)) - return; - if (!decode_config3(c)) - return; + ok = decode_config0(c); /* Read Config registers. */ + BUG_ON(!ok); /* Arch spec violation! */ + if (ok) + ok = decode_config1(c); + if (ok) + ok = decode_config2(c); + if (ok) + ok = decode_config3(c); + + mips_probe_watch_registers(c); } #ifdef CONFIG_CPU_MIPSR2 @@ -678,7 +681,6 @@ static inline void spram_config(void) {} static inline void cpu_probe_mips(struct cpuinfo_mips *c) { decode_configs(c); - mips_probe_watch_registers(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; -- cgit v1.2.3 From 255a12fbf994664125983e389c975b4403aea167 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Wed, 29 Oct 2008 14:21:32 -0700 Subject: MIPS: Use the new byteorder headers Signed-off-by: Harvey Harrison Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle --- arch/mips/include/asm/byteorder.h | 40 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index fe7dc2d59b6..2988d29a086 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -11,11 +11,19 @@ #include #include -#ifdef __GNUC__ +#if defined(__MIPSEB__) +# define __BIG_ENDIAN +#elif defined(__MIPSEL__) +# define __LITTLE_ENDIAN +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#define __SWAB_64_THRU_32__ #ifdef CONFIG_CPU_MIPSR2 -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( " wsbh %0, %1 \n" @@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return x; } -#define __arch__swab16(x) ___arch__swab16(x) +#define __arch_swab16 __arch_swab16 -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( " wsbh %0, %1 \n" @@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) return x; } -#define __arch__swab32(x) ___arch__swab32(x) +#define __arch_swab32 __arch_swab32 #ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" @@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) return x; } - -#define __arch__swab64(x) ___arch__swab64(x) - +#define __arch_swab64 __arch_swab64 #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include -#elif defined(__MIPSEL__) -# include -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif +#include #endif /* _ASM_BYTEORDER_H */ -- cgit v1.2.3 From cea7e2dfdef53fe55f359d00da562a268be06fd2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Oct 2008 13:38:45 +0000 Subject: MIPS: Sort out CPU type to name translation. As noticed by David Daney , the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 225 +++++++++++++++++++------------------------ 1 file changed, 98 insertions(+), 127 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 41a1d07b475..c9207b5fd92 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void) #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) -static inline void cpu_probe_legacy(struct cpuinfo_mips *c) +static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { switch (c->processor_id & 0xff00) { case PRID_IMP_R2000: c->cputype = CPU_R2000; + __cpu_name[cpu] = "R2000"; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) c->tlbsize = 64; break; case PRID_IMP_R3000: - if ((c->processor_id & 0xff) == PRID_REV_R3000A) - if (cpu_has_confreg()) + if ((c->processor_id & 0xff) == PRID_REV_R3000A) { + if (cpu_has_confreg()) { c->cputype = CPU_R3081E; - else + __cpu_name[cpu] = "R3081"; + } else { c->cputype = CPU_R3000A; - else + __cpu_name[cpu] = "R3000A"; + } + break; + } else { c->cputype = CPU_R3000; + __cpu_name[cpu] = "R3000"; + } c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; - else + __cpu_name[cpu] = "R4400PC"; + } else { c->cputype = CPU_R4000PC; + __cpu_name[cpu] = "R4000PC"; + } } else { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400SC; - else + __cpu_name[cpu] = "R4400SC"; + } else { c->cputype = CPU_R4000SC; + __cpu_name[cpu] = "R4000SC"; + } } c->isa_level = MIPS_CPU_ISA_III; @@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; + __cpu_name[cpu] = "NEC VR4111"; break; case PRID_REV_VR4121: c->cputype = CPU_VR4121; + __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: - if ((c->processor_id & 0xf) < 0x3) + if ((c->processor_id & 0xf) < 0x3) { c->cputype = CPU_VR4122; - else + __cpu_name[cpu] = "NEC VR4122"; + } else { c->cputype = CPU_VR4181A; + __cpu_name[cpu] = "NEC VR4181A"; + } break; case PRID_REV_VR4130: - if ((c->processor_id & 0xf) < 0x4) + if ((c->processor_id & 0xf) < 0x4) { c->cputype = CPU_VR4131; - else + __cpu_name[cpu] = "NEC VR4131"; + } else { c->cputype = CPU_VR4133; + __cpu_name[cpu] = "NEC VR4133"; + } break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; + __cpu_name[cpu] = "NEC Vr41xx"; break; } c->isa_level = MIPS_CPU_ISA_III; @@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4300: c->cputype = CPU_R4300; + __cpu_name[cpu] = "R4300"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4600: c->cputype = CPU_R4600; + __cpu_name[cpu] = "R4600"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; + __cpu_name[cpu] = "R4650"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; @@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; + __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { switch (c->processor_id & 0xff) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; + __cpu_name[cpu] = "TX3912"; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922; + __cpu_name[cpu] = "TX3922"; c->tlbsize = 64; break; - default: - c->cputype = CPU_UNKNOWN; - break; } } break; case PRID_IMP_R4700: c->cputype = CPU_R4700; + __cpu_name[cpu] = "R4700"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_TX49: c->cputype = CPU_TX49XX; + __cpu_name[cpu] = "R49XX"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_LLSC; if (!(c->processor_id & 0x08)) @@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5000: c->cputype = CPU_R5000; + __cpu_name[cpu] = "R5000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5432: c->cputype = CPU_R5432; + __cpu_name[cpu] = "R5432"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5500: c->cputype = CPU_R5500; + __cpu_name[cpu] = "R5500"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_NEVADA: c->cputype = CPU_NEVADA; + __cpu_name[cpu] = "Nevada"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; @@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000: c->cputype = CPU_R6000; + __cpu_name[cpu] = "R6000"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000A: c->cputype = CPU_R6000A; + __cpu_name[cpu] = "R6000A"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM7000: c->cputype = CPU_RM7000; + __cpu_name[cpu] = "RM7000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM9000: c->cputype = CPU_RM9000; + __cpu_name[cpu] = "RM9000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R8000: c->cputype = CPU_R8000; + __cpu_name[cpu] = "RM8000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R10000: c->cputype = CPU_R10000; + __cpu_name[cpu] = "R10000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R12000: c->cputype = CPU_R12000; + __cpu_name[cpu] = "R12000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R14000: c->cputype = CPU_R14000; + __cpu_name[cpu] = "R14000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_LOONGSON2: c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | @@ -678,51 +718,62 @@ extern void spram_config(void); static inline void spram_config(void) {} #endif -static inline void cpu_probe_mips(struct cpuinfo_mips *c) +static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; + __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KSC: case PRID_IMP_4KSD: c->cputype = CPU_4KSC; + __cpu_name[cpu] = "MIPS 4KSc"; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; + __cpu_name[cpu] = "MIPS 5Kc"; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; + __cpu_name[cpu] = "MIPS 20Kc"; break; case PRID_IMP_24K: case PRID_IMP_24KE: c->cputype = CPU_24K; + __cpu_name[cpu] = "MIPS 24Kc"; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; + __cpu_name[cpu] = "MIPS 25Kc"; break; case PRID_IMP_34K: c->cputype = CPU_34K; + __cpu_name[cpu] = "MIPS 34Kc"; break; case PRID_IMP_74K: c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 74Kc"; break; case PRID_IMP_1004K: c->cputype = CPU_1004K; + __cpu_name[cpu] = "MIPS 1004Kc"; break; } spram_config(); } -static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) +static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { @@ -731,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) switch ((c->processor_id >> 24) & 0xff) { case 0: c->cputype = CPU_AU1000; + __cpu_name[cpu] = "Au1000"; break; case 1: c->cputype = CPU_AU1500; + __cpu_name[cpu] = "Au1500"; break; case 2: c->cputype = CPU_AU1100; + __cpu_name[cpu] = "Au1100"; break; case 3: c->cputype = CPU_AU1550; + __cpu_name[cpu] = "Au1550"; break; case 4: c->cputype = CPU_AU1200; - if (2 == (c->processor_id & 0xff)) + __cpu_name[cpu] = "Au1200"; + if ((c->processor_id & 0xff) == 2) { c->cputype = CPU_AU1250; + __cpu_name[cpu] = "Au1250"; + } break; case 5: c->cputype = CPU_AU1210; + __cpu_name[cpu] = "Au1210"; break; default: panic("Unknown Au Core!"); @@ -757,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) } } -static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) +static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; + __cpu_name[cpu] = "SiByte SB1"; /* FPU in pass1 is known to have issues. */ if ((c->processor_id & 0xff) < 0x02) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: c->cputype = CPU_SB1A; + __cpu_name[cpu] = "SiByte SB1A"; break; } } -static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) +static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; + __cpu_name[cpu] = "Sandcraft SR71000"; c->scache.ways = 8; c->tlbsize = 64; break; } } -static inline void cpu_probe_nxp(struct cpuinfo_mips *c) +static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; + __cpu_name[cpu] = "Philips PR4450"; c->isa_level = MIPS_CPU_ISA_M32R1; break; - default: - panic("Unknown NXP Core!"); /* REVISIT: die? */ - break; } } - -static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_BCM3302: c->cputype = CPU_BCM3302; + __cpu_name[cpu] = "Broadcom BCM3302"; break; case PRID_IMP_BCM4710: c->cputype = CPU_BCM4710; - break; - default: - c->cputype = CPU_UNKNOWN; + __cpu_name[cpu] = "Broadcom BCM4710"; break; } } const char *__cpu_name[NR_CPUS]; -/* - * Name a CPU - */ -static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) -{ - const char *name = NULL; - - switch (c->cputype) { - case CPU_UNKNOWN: name = "unknown"; break; - case CPU_R2000: name = "R2000"; break; - case CPU_R3000: name = "R3000"; break; - case CPU_R3000A: name = "R3000A"; break; - case CPU_R3041: name = "R3041"; break; - case CPU_R3051: name = "R3051"; break; - case CPU_R3052: name = "R3052"; break; - case CPU_R3081: name = "R3081"; break; - case CPU_R3081E: name = "R3081E"; break; - case CPU_R4000PC: name = "R4000PC"; break; - case CPU_R4000SC: name = "R4000SC"; break; - case CPU_R4000MC: name = "R4000MC"; break; - case CPU_R4200: name = "R4200"; break; - case CPU_R4400PC: name = "R4400PC"; break; - case CPU_R4400SC: name = "R4400SC"; break; - case CPU_R4400MC: name = "R4400MC"; break; - case CPU_R4600: name = "R4600"; break; - case CPU_R6000: name = "R6000"; break; - case CPU_R6000A: name = "R6000A"; break; - case CPU_R8000: name = "R8000"; break; - case CPU_R10000: name = "R10000"; break; - case CPU_R12000: name = "R12000"; break; - case CPU_R14000: name = "R14000"; break; - case CPU_R4300: name = "R4300"; break; - case CPU_R4650: name = "R4650"; break; - case CPU_R4700: name = "R4700"; break; - case CPU_R5000: name = "R5000"; break; - case CPU_R5000A: name = "R5000A"; break; - case CPU_R4640: name = "R4640"; break; - case CPU_NEVADA: name = "Nevada"; break; - case CPU_RM7000: name = "RM7000"; break; - case CPU_RM9000: name = "RM9000"; break; - case CPU_R5432: name = "R5432"; break; - case CPU_4KC: name = "MIPS 4Kc"; break; - case CPU_5KC: name = "MIPS 5Kc"; break; - case CPU_R4310: name = "R4310"; break; - case CPU_SB1: name = "SiByte SB1"; break; - case CPU_SB1A: name = "SiByte SB1A"; break; - case CPU_TX3912: name = "TX3912"; break; - case CPU_TX3922: name = "TX3922"; break; - case CPU_TX3927: name = "TX3927"; break; - case CPU_AU1000: name = "Au1000"; break; - case CPU_AU1500: name = "Au1500"; break; - case CPU_AU1100: name = "Au1100"; break; - case CPU_AU1550: name = "Au1550"; break; - case CPU_AU1200: name = "Au1200"; break; - case CPU_AU1210: name = "Au1210"; break; - case CPU_AU1250: name = "Au1250"; break; - case CPU_4KEC: name = "MIPS 4KEc"; break; - case CPU_4KSC: name = "MIPS 4KSc"; break; - case CPU_VR41XX: name = "NEC Vr41xx"; break; - case CPU_R5500: name = "R5500"; break; - case CPU_TX49XX: name = "TX49xx"; break; - case CPU_20KC: name = "MIPS 20Kc"; break; - case CPU_24K: name = "MIPS 24K"; break; - case CPU_25KF: name = "MIPS 25Kf"; break; - case CPU_34K: name = "MIPS 34K"; break; - case CPU_1004K: name = "MIPS 1004K"; break; - case CPU_74K: name = "MIPS 74K"; break; - case CPU_VR4111: name = "NEC VR4111"; break; - case CPU_VR4121: name = "NEC VR4121"; break; - case CPU_VR4122: name = "NEC VR4122"; break; - case CPU_VR4131: name = "NEC VR4131"; break; - case CPU_VR4133: name = "NEC VR4133"; break; - case CPU_VR4181: name = "NEC VR4181"; break; - case CPU_VR4181A: name = "NEC VR4181A"; break; - case CPU_SR71000: name = "Sandcraft SR71000"; break; - case CPU_BCM3302: name = "Broadcom BCM3302"; break; - case CPU_BCM4710: name = "Broadcom BCM4710"; break; - case CPU_PR4450: name = "Philips PR4450"; break; - case CPU_LOONGSON2: name = "ICT Loongson-2"; break; - default: - BUG(); - } - - return name; -} - __cpuinit void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -917,30 +889,31 @@ __cpuinit void cpu_probe(void) c->processor_id = read_c0_prid(); switch (c->processor_id & 0xff0000) { case PRID_COMP_LEGACY: - cpu_probe_legacy(c); + cpu_probe_legacy(c, cpu); break; case PRID_COMP_MIPS: - cpu_probe_mips(c); + cpu_probe_mips(c, cpu); break; case PRID_COMP_ALCHEMY: - cpu_probe_alchemy(c); + cpu_probe_alchemy(c, cpu); break; case PRID_COMP_SIBYTE: - cpu_probe_sibyte(c); + cpu_probe_sibyte(c, cpu); break; case PRID_COMP_BROADCOM: - cpu_probe_broadcom(c); + cpu_probe_broadcom(c, cpu); break; case PRID_COMP_SANDCRAFT: - cpu_probe_sandcraft(c); + cpu_probe_sandcraft(c, cpu); break; case PRID_COMP_NXP: - cpu_probe_nxp(c); + cpu_probe_nxp(c, cpu); break; - default: - c->cputype = CPU_UNKNOWN; } + BUG_ON(!__cpu_name[cpu]); + BUG_ON(c->cputype == CPU_UNKNOWN); + /* * Platform code can force the cpu type to optimize code * generation. In that case be sure the cpu type is correctly @@ -960,8 +933,6 @@ __cpuinit void cpu_probe(void) } } - __cpu_name[cpu] = cpu_to_name(c); - if (cpu_has_mips_r2) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else -- cgit v1.2.3 From 4bdebe5b4a7216bd6bfca9e9b368abad8e9f9bd9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 26 Oct 2008 16:12:13 +0000 Subject: CHAR: Delete old and now unused DS1286 driver. It was only used by two SGI platforms which recently were converted to RTC_LIB and with RTC_LIB enabled the legacy drivers are no more selectable. Signed-off-by: Ralf Baechle Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig | 5 ----- arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip28_defconfig | 2 -- arch/mips/include/asm/ds1286.h | 15 --------------- 4 files changed, 23 deletions(-) delete mode 100644 arch/mips/include/asm/ds1286.h (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 653574bc19c..f4af967a6b3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -327,7 +327,6 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -382,7 +381,6 @@ config SGI_IP28 select HW_HAS_EISA select I8253 select I8259 - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -893,9 +891,6 @@ config EMMA2RH config SERIAL_RM9000 bool -config SGI_HAS_DS1286 - bool - config SGI_HAS_INDYDOG bool diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index cc8e6bf2b24..f719bf5e01a 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -771,7 +771,6 @@ CONFIG_WATCHDOG=y CONFIG_INDYDOG=m # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set -CONFIG_SGI_DS1286=m # CONFIG_R3964 is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 822b01f643e..70a744e9a8c 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y -CONFIG_SGI_HAS_DS1286=y CONFIG_SGI_HAS_INDYDOG=y CONFIG_SGI_HAS_SEEQ=y CONFIG_SGI_HAS_WD93=y @@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set -CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h deleted file mode 100644 index 6983b6ff0af..00000000000 --- a/arch/mips/include/asm/ds1286.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_DS1286_H -#define _ASM_DS1286_H - -#include - -#endif /* _ASM_DS1286_H */ -- cgit v1.2.3 From 09d9327b3420002c9952a81db37effec9dc1135e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 27 Oct 2008 13:10:29 +0000 Subject: CHAR: Delete old and now unused M48T35 RTC driver for SGI IP27. It was only used by this one SGI platform which recently was converted to RTC_LIB and with RTC_LIB enabled the legacy drivers are no more selectable. Signed-off-by: Ralf Baechle --- arch/mips/configs/ip27_defconfig | 1 - arch/mips/include/asm/m48t35.h | 27 --------------------------- 2 files changed, 28 deletions(-) delete mode 100644 arch/mips/include/asm/m48t35.h (limited to 'arch') diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 831d3e5a1ea..34ea319be94 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=m # CONFIG_RTC is not set -CONFIG_SGI_IP27_RTC=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_DRM is not set diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h deleted file mode 100644 index f44852e9a96..00000000000 --- a/arch/mips/include/asm/m48t35.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip - */ -#ifndef _ASM_M48T35_H -#define _ASM_M48T35_H - -#include - -extern spinlock_t rtc_lock; - -struct m48t35_rtc { - volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */ - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T35_RTC_SET 0x80 -#define M48T35_RTC_STOPPED 0x80 -#define M48T35_RTC_READ 0x40 - -#endif /* _ASM_M48T35_H */ -- cgit v1.2.3 From eadefeff9c5572d82c2f5d907a0bfb3ba55ce901 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 15 Oct 2008 09:50:23 +0200 Subject: [ARM] MX3: Use ioremap wrapper to map SoC devices nonshared The internal devices of the MX3 Processor have to be mapped MT_DEVICE_NONSHARED devices, otherwise cache corruptions occur. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/io.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 65b6810124c..5d4cb119644 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -14,6 +14,26 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff +#ifdef CONFIG_ARCH_MX3 +#define __arch_ioremap __mx3_ioremap +#define __arch_iounmap __iounmap + +static inline void __iomem * +__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) +{ + if (mtype == MT_DEVICE) { + /* Access all peripherals below 0x80000000 as nonshared device + * but leave l2cc alone. + */ + if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) || + (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE))) + mtype = MT_DEVICE_NONSHARED; + } + + return __arm_ioremap(phys_addr, size, mtype); +} +#endif + /* io address mapping macro */ #define __io(a) ((void __iomem *)(a)) -- cgit v1.2.3 From 5cac9d6558009d0fcdb7a0f38247ca578c8c685b Mon Sep 17 00:00:00 2001 From: Darius Augulis Date: Wed, 15 Oct 2008 10:38:30 +0200 Subject: [ARM] MXC: Fix mxc_gpio_get(), which must read PSR register instead DR. The Data register holds the value we have written to a gpio. To get the input value we must read the Pad Status Register MX3 (or Sample Status register in MX1/2 terms) Signed-off-by: Darius Augulis Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 733e0acac91..de5c4747453 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -188,7 +188,7 @@ static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset) struct mxc_gpio_port *port = container_of(chip, struct mxc_gpio_port, chip); - return (__raw_readl(port->base + GPIO_DR) >> offset) & 1; + return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1; } static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -- cgit v1.2.3 From 2eca047b289307594d0d6ce62c8237fa9c5b9b5e Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 17 Oct 2008 16:10:38 +0200 Subject: [ARM] mx31ads: Add missing include mx31ads_defconfig compilation failed with arch/arm/mach-mx3/mx31ads.c: In function 'mxc_init_imx_uart': arch/arm/mach-mx3/mx31ads.c:102: error: 'mxc_uart_device0' undeclared (first use in this function) arch/arm/mach-mx3/mx31ads.c:102: error: (Each undeclared identifier is reported only once arch/arm/mach-mx3/mx31ads.c:102: error: for each function it appears in.) make[1]: *** [arch/arm/mach-mx3/mx31ads.o] Error 1 Add missing include Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31ads.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index 1be4a390c63..f902a7c37c3 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -35,6 +35,8 @@ #include #include +#include "devices.h" + /*! * @file mx31ads.c * -- cgit v1.2.3 From b73b925a6b9d69478c6ae4e74ef20607fd24aeaa Mon Sep 17 00:00:00 2001 From: Sergey Lapin Date: Mon, 27 Oct 2008 07:43:45 +0100 Subject: [ARM] 5326/1: AFEB9260: Fix for i2c_board_info structure i2c_board_info array was filled incorrectly. Due to circumstances, the way it is filled works. This patch fills array properly. Signed-off-by: Sergey Lapin Signed-off-by: Russell King --- arch/arm/mach-at91/board-afeb-9260v1.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 9c040c78889..e263fda3e2d 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -165,6 +165,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = { static struct i2c_board_info __initdata afeb9260_i2c_devices[] = { { I2C_BOARD_INFO("fm3130", 0x68), + }, { I2C_BOARD_INFO("24c64", 0x50), }, }; -- cgit v1.2.3 From c17dad6905fc82d8f523399e5c3f014e81d61df6 Mon Sep 17 00:00:00 2001 From: Alexey Dobriyan Date: Wed, 29 Oct 2008 14:00:50 -0700 Subject: .gitignore updates Signed-off-by: Alexey Dobriyan Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/x86/boot/compressed/.gitignore | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/boot/compressed/.gitignore b/arch/x86/boot/compressed/.gitignore index be0ed065249..63eff3b04d0 100644 --- a/arch/x86/boot/compressed/.gitignore +++ b/arch/x86/boot/compressed/.gitignore @@ -1 +1,3 @@ relocs +vmlinux.bin.all +vmlinux.relocs -- cgit v1.2.3 From c08b6acc9b996ba6231105cb12a4125c957e0c97 Mon Sep 17 00:00:00 2001 From: Mike Travis Date: Thu, 30 Oct 2008 11:33:19 -0700 Subject: x86, uv: fix compile error in uv_hub.h Impact: include file dependency cleanup Fix compile errors of files that include asm/uv/uv_hub.h but do not include linux/timer.h. [ such files are not mainline right now. ] Signed-of-by: Mike Travis Signed-off-by: Ingo Molnar --- arch/x86/include/asm/uv/uv_hub.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index c6ad93e315c..7a5782610b2 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -13,6 +13,7 @@ #include #include +#include #include #include -- cgit v1.2.3 From 08c33308575b370c89b4ed1198ece5f93145a2aa Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Thu, 30 Oct 2008 16:08:38 -0500 Subject: x86/voyager: fix boot breakage caused by x86: boot secondary cpus through initial_code Impact: boot up secondary CPUs as well on x86/Voyager systems This commit: | commit 3e9704739daf46a8ba6593d749c67b5f7cd633d2 | Author: Glauber Costa | Date: Wed May 28 13:01:54 2008 -0300 | | x86: boot secondary cpus through initial_code removed the use of initialize_secondary. However, it didn't update voyager, so the secondary cpus no longer boot. Fix this by adding the initial_code switch to voyager as well. Signed-off-by: James Bottomley Cc: Glauber Costa Signed-off-by: Ingo Molnar --- arch/x86/mach-voyager/voyager_smp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c index 0f6e8a6523a..9cd327a278a 100644 --- a/arch/x86/mach-voyager/voyager_smp.c +++ b/arch/x86/mach-voyager/voyager_smp.c @@ -90,6 +90,7 @@ static void ack_vic_irq(unsigned int irq); static void vic_enable_cpi(void); static void do_boot_cpu(__u8 cpuid); static void do_quad_bootstrap(void); +static void initialize_secondary(void); int hard_smp_processor_id(void); int safe_smp_processor_id(void); @@ -650,6 +651,8 @@ void __init smp_boot_cpus(void) smp_tune_scheduling(); */ smp_store_cpu_info(boot_cpu_id); + /* setup the jump vector */ + initial_code = (unsigned long)initialize_secondary; printk("CPU%d: ", boot_cpu_id); print_cpu_info(&cpu_data(boot_cpu_id)); @@ -702,7 +705,7 @@ void __init smp_boot_cpus(void) /* Reload the secondary CPUs task structure (this function does not * return ) */ -void __init initialize_secondary(void) +static void __init initialize_secondary(void) { #if 0 // AC kernels only -- cgit v1.2.3 From 017d9d20d88cacb0a6a29f343b23c95e203f6645 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Thu, 30 Oct 2008 16:05:39 -0500 Subject: x86: use CONFIG_X86_SMP instead of CONFIG_SMP Impact: fix x86/Voyager boot CONFIG_SMP is used for features which work on *all* x86 boxes. CONFIG_X86_SMP is used for standard PC like x86 boxes (for things like multi core and apics) Signed-off-by: James Bottomley Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/addon_cpuid_features.c | 2 +- arch/x86/kernel/tsc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c index 0d9c993aa93..ef8f831af82 100644 --- a/arch/x86/kernel/cpu/addon_cpuid_features.c +++ b/arch/x86/kernel/cpu/addon_cpuid_features.c @@ -69,7 +69,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) */ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c) { -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_SMP unsigned int eax, ebx, ecx, edx, sub_index; unsigned int ht_mask_width, core_plus_mask_width; unsigned int core_select_mask, core_level_siblings; diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 161bb850fc4..62348e4fd8d 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -759,7 +759,7 @@ __cpuinit int unsynchronized_tsc(void) if (!cpu_has_tsc || tsc_unstable) return 1; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_SMP if (apic_is_clustered_box()) return 1; #endif -- cgit v1.2.3 From ee477524b461324ed8fc950f451c3671dc79f12e Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Thu, 30 Oct 2008 16:28:35 -0500 Subject: x86/voyager: fix compile breakage casued by x86: move prefill_possible_map calling early Impact: fix build failure on x86/Voyager Before: | commit 329513a35d1a2b6b28d54f5c2c0dde4face8200b | Author: Yinghai Lu | Date: Wed Jul 2 18:54:40 2008 -0700 | | x86: move prefill_possible_map calling early prefill_possible_mask() was hidden under CONFIG_HOTPLUG_CPU rendering it invisitble to voyager. Since this commit it's exposed, but not provided by the voyager subarch, so add a dummy stub to fix the link breakage. Signed-off-by: James Bottomley Cc: Yinghai Lu Signed-off-by: Ingo Molnar --- arch/x86/mach-voyager/voyager_smp.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c index 9cd327a278a..01285af5782 100644 --- a/arch/x86/mach-voyager/voyager_smp.c +++ b/arch/x86/mach-voyager/voyager_smp.c @@ -345,6 +345,12 @@ static void do_quad_bootstrap(void) } } +void prefill_possible_map(void) +{ + /* This is empty on voyager because we need a much + * earlier detection which is done in find_smp_config */ +} + /* Set up all the basic stuff: read the SMP config and make all the * SMP information reflect only the boot cpu. All others will be * brought on-line later. */ -- cgit v1.2.3 From 9e41bff2708e420e61e6b89a54c15232857069b1 Mon Sep 17 00:00:00 2001 From: Ravikiran G Thirumalai Date: Thu, 30 Oct 2008 13:59:21 -0700 Subject: x86: fix /dev/mem mmap breakage when PAT is disabled Impact: allow /dev/mem mmaps on non-PAT CPUs/platforms Fix mmap to /dev/mem when CONFIG_X86_PAT is off and CONFIG_STRICT_DEVMEM is off mmap to /dev/mem on kernel memory has been failing since the introduction of PAT (CONFIG_STRICT_DEVMEM=n case). Seems like the check to avoid cache aliasing with PAT is kicking in even when PAT is disabled. The bug seems to have crept in 2.6.26. This patch makes sure that the mmap to regular kernel memory succeeds if CONFIG_STRICT_DEVMEM=n and PAT is disabled, and the checks to avoid cache aliasing still happens if PAT is enabled. Signed-off-by: Ravikiran Thirumalai Tested-by: Tim Sirianni Cc: Acked-by: H. Peter Anvin Signed-off-by: Ingo Molnar --- arch/x86/mm/pat.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index 738fd0f2495..eb1bf000d12 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -481,12 +481,16 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size) return 1; } #else +/* This check is needed to avoid cache aliasing when PAT is enabled */ static inline int range_is_allowed(unsigned long pfn, unsigned long size) { u64 from = ((u64)pfn) << PAGE_SHIFT; u64 to = from + size; u64 cursor = from; + if (!pat_enabled) + return 1; + while (cursor < to) { if (!devmem_is_allowed(pfn)) { printk(KERN_INFO -- cgit v1.2.3 From b3572e361b6b2ac5e724bc4bb932b7774b720b95 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Thu, 30 Oct 2008 16:00:59 -0500 Subject: x86/voyager: fix compile breakage caused by dc1e35c6e95e8923cf1d3510438b63c600fee1e2 Impact: build fix on x86/Voyager Given commits like this: | Author: Suresh Siddha | Date: Tue Jul 29 10:29:19 2008 -0700 | | x86, xsave: enable xsave/xrstor on cpus with xsave support Which deliberately expose boot cpu dependence to pieces of the system, I think it's time to explicitly have a variable for it to prevent this continual misassumption that the boot CPU is zero. Signed-off-by: James Bottomley Signed-off-by: Ingo Molnar --- arch/x86/Kconfig | 4 ++++ arch/x86/include/asm/smp.h | 6 ++++++ arch/x86/kernel/cpu/common.c | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 350bee1d54d..2a40c4c6dd7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -231,6 +231,10 @@ config SMP If you don't know what to do here, say N. +config X86_HAS_BOOT_CPU_ID + def_bool y + depends on X86_VOYAGER + config X86_FIND_SMP_CONFIG def_bool y depends on X86_MPPARSE || X86_VOYAGER diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 2766021aef8..d12811ce51d 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -225,5 +225,11 @@ static inline int hard_smp_processor_id(void) #endif /* CONFIG_X86_LOCAL_APIC */ +#ifdef CONFIG_X86_HAS_BOOT_CPU_ID +extern unsigned char boot_cpu_id; +#else +#define boot_cpu_id 0 +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_SMP_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 25581dcb280..93e9393ea64 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1134,7 +1134,7 @@ void __cpuinit cpu_init(void) /* * Boot processor to setup the FP and extended state context info. */ - if (!smp_processor_id()) + if (smp_processor_id() == boot_cpu_id) init_thread_xstate(); xsave_init(); -- cgit v1.2.3 From bfcb4c1becf93b1592f4a03a4d6e00a3ab89d5ec Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Thu, 30 Oct 2008 16:13:37 -0500 Subject: x86/voyager: fix missing cpu_index initialisation Impact: fix /proc/cpuinfo output on x86/Voyager Ever since | commit 92cb7612aee39642d109b8d935ad265e602c0563 | Author: Mike Travis | Date: Fri Oct 19 20:35:04 2007 +0200 | | x86: convert cpuinfo_x86 array to a per_cpu array We've had an extra field in cpuinfo_x86 which is cpu_index. Unfortunately, voyager has never initialised this, although the only noticeable impact seems to be that /proc/cpuinfo shows all zeros for the processor ids. Anyway, fix this by initialising the boot CPU properly and setting the index when the secondaries update. Signed-off-by: James Bottomley Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/common.c | 2 ++ arch/x86/mach-voyager/voyager_smp.c | 1 + 2 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 93e9393ea64..da8f15ac7a6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -549,6 +549,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) this_cpu->c_early_init(c); validate_pat_support(c); + + c->cpu_index = boot_cpu_id; } void __init early_cpu_init(void) diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c index 01285af5782..7f4c6af1435 100644 --- a/arch/x86/mach-voyager/voyager_smp.c +++ b/arch/x86/mach-voyager/voyager_smp.c @@ -420,6 +420,7 @@ void __init smp_store_cpu_info(int id) struct cpuinfo_x86 *c = &cpu_data(id); *c = boot_cpu_data; + c->cpu_index = id; identify_secondary_cpu(c); } -- cgit v1.2.3 From 1c4acdb467f8a6704855a5670ff3d82e3c18eb0b Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Fri, 31 Oct 2008 00:43:03 +0100 Subject: x86: cpu_index build fix fix: arch/x86/kernel/cpu/common.c: In function 'early_identify_cpu': arch/x86/kernel/cpu/common.c:553: error: 'struct cpuinfo_x86' has no member named 'cpu_index' as cpu_index is only available on SMP. Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index da8f15ac7a6..003a65395bd 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -550,7 +550,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) validate_pat_support(c); +#ifdef CONFIG_SMP c->cpu_index = boot_cpu_id; +#endif } void __init early_cpu_init(void) -- cgit v1.2.3 From ad5173ff8a387191dbacf889becb92c59aba5d59 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Fri, 31 Oct 2008 11:24:27 -0500 Subject: lguest: fix early_ioremap. dmi_scan_machine breaks under lguest: lguest: unhandled trap 14 at 0xc04edeae (0xffa00000) This is because we use current_cr3 for the read_cr3() paravirt function, and it isn't set until the first cr3 change. We got away with it until this happened. Signed-off-by: Rusty Russell --- arch/x86/lguest/boot.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 48ee4f9435f..4e22fa08d62 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -367,10 +367,9 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx, * lazily after a task switch, and Linux uses that gratefully, but wouldn't a * name like "FPUTRAP bit" be a little less cryptic? * - * We store cr0 (and cr3) locally, because the Host never changes it. The - * Guest sometimes wants to read it and we'd prefer not to bother the Host - * unnecessarily. */ -static unsigned long current_cr0, current_cr3; + * We store cr0 locally because the Host never changes it. The Guest sometimes + * wants to read it and we'd prefer not to bother the Host unnecessarily. */ +static unsigned long current_cr0; static void lguest_write_cr0(unsigned long val) { lazy_hcall(LHCALL_TS, val & X86_CR0_TS, 0, 0); @@ -399,17 +398,23 @@ static unsigned long lguest_read_cr2(void) return lguest_data.cr2; } +/* See lguest_set_pte() below. */ +static bool cr3_changed = false; + /* cr3 is the current toplevel pagetable page: the principle is the same as - * cr0. Keep a local copy, and tell the Host when it changes. */ + * cr0. Keep a local copy, and tell the Host when it changes. The only + * difference is that our local copy is in lguest_data because the Host needs + * to set it upon our initial hypercall. */ static void lguest_write_cr3(unsigned long cr3) { + lguest_data.pgdir = cr3; lazy_hcall(LHCALL_NEW_PGTABLE, cr3, 0, 0); - current_cr3 = cr3; + cr3_changed = true; } static unsigned long lguest_read_cr3(void) { - return current_cr3; + return lguest_data.pgdir; } /* cr4 is used to enable and disable PGE, but we don't care. */ @@ -498,13 +503,13 @@ static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval) * to forget all of them. Fortunately, this is very rare. * * ... except in early boot when the kernel sets up the initial pagetables, - * which makes booting astonishingly slow. So we don't even tell the Host - * anything changed until we've done the first page table switch. */ + * which makes booting astonishingly slow: 1.83 seconds! So we don't even tell + * the Host anything changed until we've done the first page table switch, + * which brings boot back to 0.25 seconds. */ static void lguest_set_pte(pte_t *ptep, pte_t pteval) { *ptep = pteval; - /* Don't bother with hypercall before initial setup. */ - if (current_cr3) + if (cr3_changed) lazy_hcall(LHCALL_FLUSH_TLB, 1, 0, 0); } @@ -521,7 +526,7 @@ static void lguest_set_pte(pte_t *ptep, pte_t pteval) static void lguest_flush_tlb_single(unsigned long addr) { /* Simply set it to zero: if it was not, it will fault back in. */ - lazy_hcall(LHCALL_SET_PTE, current_cr3, addr, 0); + lazy_hcall(LHCALL_SET_PTE, lguest_data.pgdir, addr, 0); } /* This is what happens after the Guest has removed a large number of entries. -- cgit v1.2.3 From 526e5ab200ce483dcdf146806f4936bd58daa800 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Fri, 31 Oct 2008 11:24:27 -0500 Subject: lguest: fix irq vectors. do_IRQ: cannot handle IRQ -1 vector 0x20 cpu 0 ------------[ cut here ]------------ kernel BUG at arch/x86/kernel/irq_32.c:219! We're not ISA: we have a 1:1 mapping from vectors to irqs. Signed-off-by: Rusty Russell --- arch/x86/lguest/boot.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 4e22fa08d62..a5d8e1ace1c 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c @@ -586,6 +586,9 @@ static void __init lguest_init_IRQ(void) for (i = 0; i < LGUEST_IRQS; i++) { int vector = FIRST_EXTERNAL_VECTOR + i; + /* Some systems map "vectors" to interrupts weirdly. Lguest has + * a straightforward 1 to 1 mapping, so force that here. */ + __get_cpu_var(vector_irq)[vector] = i; if (vector != SYSCALL_VECTOR) { set_intr_gate(vector, interrupt[vector]); set_irq_chip_and_handler_name(i, &lguest_irq_controller, -- cgit v1.2.3