From 553bd149bb2de7848b2b84642876f27202421368 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Wed, 2 Sep 2009 10:57:52 +0800 Subject: drm/i915: fix tiling on IGDNG It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: Zhenyu Wang Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/i915_gem_tiling.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c') diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b22ec..e774a4a1a50 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; bool need_disable; - if (!IS_I9XX(dev)) { + if (IS_IGDNG(dev)) { + /* On IGDNG whatever DRAM config, GPU always do + * same swizzling setup. + */ + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else if (!IS_I9XX(dev)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } - /* FIXME: check with memory config on IGDNG */ - if (IS_IGDNG(dev)) { - DRM_ERROR("disable tiling on IGDNG...\n"); - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - } - dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; } -- cgit v1.2.3