From 32b3c2abaf8c61c80a8b02071c73f05252122ffe Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Fri, 26 Feb 2010 19:14:12 +0000 Subject: drm/radeon/kms: initialize set_surface_reg reg for rs600 asic rs600 asic was missing set_surface_reg callback leading to oops. Signed-off-by: Jerome Glisse Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_asic.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 4572a669988..d3a157b2bcb 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -407,6 +407,8 @@ static struct radeon_asic rs600_asic = { .get_pcie_lanes = NULL, .set_pcie_lanes = NULL, .set_clock_gating = &radeon_atom_set_clock_gating, + .set_surface_reg = r100_set_surface_reg, + .clear_surface_reg = r100_clear_surface_reg, .bandwidth_update = &rs600_bandwidth_update, .hpd_init = &rs600_hpd_init, .hpd_fini = &rs600_hpd_fini, -- cgit v1.2.3 From d964fc54ed06cea45dfd10832ed3d34f3ddb661b Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Thu, 25 Feb 2010 04:23:31 +0000 Subject: drm/radeon: use ALIGN instead of open coding it Cc: Jerome Glisse Cc: Alex Deucher Signed-off-by: Matt Turner Reviewed-by: Corbin Simpson Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r600_blit.c | 2 +- drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c index 5ea43234758..f4fb88ece2b 100644 --- a/drivers/gpu/drm/radeon/r600_blit.c +++ b/drivers/gpu/drm/radeon/r600_blit.c @@ -49,7 +49,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 RING_LOCALS; DRM_DEBUG("\n"); - h = (h + 7) & ~7; + h = ALIGN(h, 8); if (h < 8) h = 8; diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index de8bbbcfe11..f6c6c77db7e 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -25,7 +25,7 @@ set_render_target(struct radeon_device *rdev, int format, u32 cb_color_info; int pitch, slice; - h = (h + 7) & ~7; + h = ALIGN(h, 8); if (h < 8) h = 8; @@ -396,7 +396,7 @@ set_default_state(struct radeon_device *rdev) NUM_ES_STACK_ENTRIES(num_es_stack_entries)); /* emit an IB pointing at default state */ - dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf; + dwords = ALIGN(rdev->r600_blit.state_len, 0x10); gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); -- cgit v1.2.3 From 566d84d172161cb6c0c4dd834c34abbac6bf7b38 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 24 Feb 2010 17:17:13 +1000 Subject: drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond radeon's have a special ability to passthrough writes in their internal memory space directly to PCI, this ability means that if some of the internal surfaces like the depth buffer point at 0x0, any writes to these will go directly to RAM at 0x0 via PCI busmastering. Now mesa used to always emit clears after emitting state, since the radeon mesa driver was refactored a year or more ago, it was found it could generate a clear request without ever sending any setup state to the card. So the clear would attempt to clear the depth buffer at 0x0, which would overwrite main memory at this point. fs corruption ensues. Also once one app did this correctly, it would never get set back to 0 making this messy to reproduce. The kernel should block this from happening as mesa runs without privs, though it does require the user be connected to the current running X session. This patch implements a check to make sure the depth offset has been set before a depth clear occurs and if it finds one it prints a warning and ignores the depth clear request. There is also a mesa fix to avoid sending the badness going into mesa. This only affects r100/r200 GPUs in user modesetting mode. Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/radeon_cp.c | 1 + drivers/gpu/drm/radeon/radeon_drv.h | 2 ++ drivers/gpu/drm/radeon/radeon_state.c | 6 ++++++ 3 files changed, 9 insertions(+) (limited to 'drivers/gpu/drm') diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 06123ba31d3..dc6eba6b96d 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -1644,6 +1644,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri radeon_cp_load_microcode(dev_priv); radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); + dev_priv->have_z_offset = 0; radeon_do_engine_reset(dev); radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index f6d20cee570..ee484b61bc5 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -267,6 +267,8 @@ typedef struct drm_radeon_private { u32 scratch_ages[5]; + int have_z_offset; + /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ resource_size_t fb_aper_offset; diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c index 44b6d66b0ab..8e69dc485dc 100644 --- a/drivers/gpu/drm/radeon/radeon_state.c +++ b/drivers/gpu/drm/radeon/radeon_state.c @@ -105,6 +105,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * DRM_ERROR("Invalid depth buffer offset\n"); return -EINVAL; } + dev_priv->have_z_offset = 1; break; case RADEON_EMIT_PP_CNTL: @@ -898,6 +899,11 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev, if (tmp & RADEON_BACK) flags |= RADEON_FRONT; } + if (flags & (RADEON_DEPTH|RADEON_STENCIL)) { + if (!dev_priv->have_z_offset) + printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n"); + flags &= ~(RADEON_DEPTH | RADEON_STENCIL); + } if (flags & (RADEON_FRONT | RADEON_BACK)) { -- cgit v1.2.3