From edb81956422c9926553bb97e3e56b849da0f4bb5 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 17 Sep 2009 17:06:47 -0700 Subject: drm/i915: correct FBC update when pipe base update occurs We usually don't have an SAREA, and we always want to update the FBC status anyway, so move the update up above the various master/sarea checks. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 44234150e84..cb0f4f96439 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1260,6 +1260,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, I915_READ(dspbase); } + if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0)) + intel_update_fbc(crtc, &crtc->mode); + intel_wait_for_vblank(dev); if (old_fb) { @@ -1286,9 +1289,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, master_priv->sarea_priv->pipeA_y = y; } - if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0)) - intel_update_fbc(crtc, &crtc->mode); - return 0; } -- cgit v1.2.3