From c492dbbc420549a71cce8b0a8aea48c4a2c0e774 Mon Sep 17 00:00:00 2001 From: Thomas White Date: Tue, 10 Nov 2009 00:06:38 +0100 Subject: Add interrupt-driven waitqueue for better GPU synchronisation Signed-off-by: Thomas White --- drivers/mfd/glamo/glamo-core.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/mfd/glamo/glamo-core.c') diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c index d8ebf400180..3dcb3589084 100644 --- a/drivers/mfd/glamo/glamo-core.c +++ b/drivers/mfd/glamo/glamo-core.c @@ -198,6 +198,11 @@ static struct resource glamo_graphics_resources[] = { .start = GLAMO_REGOFS_LCD, .end = GLAMO_REGOFS_MMC - 1, .flags = IORESOURCE_MEM, + }, { + .name = "glamo-2d-regs", + .start = GLAMO_REGOFS_2D, + .end = GLAMO_REGOFS_3D- 1, + .flags = IORESOURCE_MEM, } }; @@ -349,6 +354,24 @@ static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc) } +void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq) +{ + /* set interrupt source */ + __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, irq); +} + + +void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq) +{ + u_int16_t tmp; + + /* set bit in enable register */ + tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE); + tmp |= irq; + __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp); +} + + static ssize_t regs_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -- cgit v1.2.3