From 6892914fb7980d844f2bac859f4095df9ebd18da Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Tue, 9 Aug 2005 20:17:14 -0700 Subject: [TG3]: Add indirect register method for 5703 behind ICH This patch adds the new workaround for 5703 A1/A2 if it is behind certain ICH bridges. The workaround disables memory and uses config. cycles only to access all registers. The 5702/03 chips can mistakenly decode the special cycles from the ICH chipsets as memory write cycles, causing corruption of register and memory space. Only certain ICH bridges will drive special cycles with non-zero data during the address phase which can fall within the 5703's address range. This is not an ICH bug as the PCI spec allows non-zero address during special cycles. However, only these ICH bridges are known to drive non-zero addresses during special cycles. The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh because it is used in irq handler when using the indirect method to disable interrupts. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net/tg3.h') diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index c398b8478d6..c184b773e58 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -2174,6 +2174,7 @@ struct tg3 { #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \ TG3_FLG2_MII_SERDES) #define TG3_FLG2_PARALLEL_DETECT 0x01000000 +#define TG3_FLG2_ICH_WORKAROUND 0x02000000 u32 split_mode_max_reqs; #define SPLIT_MODE_5704_MAX_REQ 3 -- cgit v1.2.3