From 40c0d87948ab635e814f45664259d4cc193651a1 Mon Sep 17 00:00:00 2001 From: Grant Grundler Date: Fri, 8 Sep 2006 11:15:37 -0700 Subject: [PATCH] Flush MMIO writes in reset sequence The obvious safe registers to read is one from PCI config space. Signed-off-by: Grant Grundler Signed-off-by: Kyle McMartin Signed-off-by: Valerie Henson Signed-off-by: Jeff Garzik --- drivers/net/tulip/tulip_core.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/net') diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c index 2f181809bde..6a7ca8695ff 100644 --- a/drivers/net/tulip/tulip_core.c +++ b/drivers/net/tulip/tulip_core.c @@ -295,12 +295,14 @@ static void tulip_up(struct net_device *dev) /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ iowrite32(0x00000001, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); /* Deassert reset. Wait the specified 50 PCI cycles after a reset by initializing Tx and Rx queues and the address filter list. */ iowrite32(tp->csr0, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); if (tulip_debug > 1) -- cgit v1.2.3