From 60083ee0c210ff1e7b5c921f5ef8d70d54634593 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Fri, 3 Jul 2009 16:08:08 +0200 Subject: Staging: rtl8192su: remove RTL8192SE ifdefs Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192su/r8192S_phy.c | 417 +-------------------------------- 1 file changed, 3 insertions(+), 414 deletions(-) (limited to 'drivers/staging/rtl8192su/r8192S_phy.c') diff --git a/drivers/staging/rtl8192su/r8192S_phy.c b/drivers/staging/rtl8192su/r8192S_phy.c index 515a56ee375..96894c402f3 100644 --- a/drivers/staging/rtl8192su/r8192S_phy.c +++ b/drivers/staging/rtl8192su/r8192S_phy.c @@ -109,12 +109,6 @@ phy_SwChnlStepByStep( ); static RT_STATUS phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType); -#ifdef RTL8192SE -static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset); -static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset); -static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); -static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); -#endif static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx); static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm); void phy_SetFwCmdIOCallback(struct net_device* dev); @@ -705,406 +699,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 } -#ifdef RTL8192SE -/*----------------------------------------------------------------------------- - * Function: phy_FwRFSerialRead() - * - * Overview: We support firmware to execute RF-R/W. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/21/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -//use in phy only -static u32 -phy_FwRFSerialRead( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset ) -{ - u32 retValue = 0; - //u32 Data = 0; - //u8 time = 0; -#if 0 - //DbgPrint("FW RF CTRL\n\r"); - /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can - not execute the scheme in the initial step. Otherwise, RF-R/W will waste - much time. This is only for site survey. */ - // 1. Read operation need not insert data. bit 0-11 - //Data &= bMask12Bits; - // 2. Write RF register address. Bit 12-19 - Data |= ((Offset&0xFF)<<12); - // 3. Write RF path. bit 20-21 - Data |= ((eRFPath&0x3)<<20); - // 4. Set RF read indicator. bit 22=0 - //Data |= 0x00000; - // 5. Trigger Fw to operate the command. bit 31 - Data |= 0x80000000; - // 6. We can not execute read operation if bit 31 is 1. - while (PlatformIORead4Byte(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-R Time=%d\n\r", time); - delay_us(10); - } - else - break; - } - // 7. Execute read operation. - PlatformIOWrite4Byte(dev, QPNR, Data); - // 8. Check if firmawre send back RF content. - while (PlatformIORead4Byte(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-W Time=%d\n\r", time); - delay_us(10); - } - else - return (0); - } - retValue = PlatformIORead4Byte(dev, RF_DATA); -#endif - return (retValue); - -} /* phy_FwRFSerialRead */ - -/*----------------------------------------------------------------------------- - * Function: phy_FwRFSerialWrite() - * - * Overview: We support firmware to execute RF-R/W. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/21/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -//use in phy only -static void -phy_FwRFSerialWrite( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset, - u32 Data ) -{ -#if 0 - u8 time = 0; - DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); - /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can - not execute the scheme in the initial step. Otherwise, RF-R/W will waste - much time. This is only for site survey. */ - - // 1. Set driver write bit and 12 bit data. bit 0-11 - //Data &= bMask12Bits; // Done by uper layer. - // 2. Write RF register address. bit 12-19 - Data |= ((Offset&0xFF)<<12); - // 3. Write RF path. bit 20-21 - Data |= ((eRFPath&0x3)<<20); - // 4. Set RF write indicator. bit 22=1 - Data |= 0x400000; - // 5. Trigger Fw to operate the command. bit 31=1 - Data |= 0x80000000; - - // 6. Write operation. We can not write if bit 31 is 1. - while (PlatformIORead4Byte(dev, QPNR)&0x80000000) - { - // If FW can not finish RF-R/W for more than ?? times. We must reset FW. - if (time++ < 100) - { - //DbgPrint("FW not finish RF-W Time=%d\n\r", time); - delay_us(10); - } - else - break; - } - // 7. No matter check bit. We always force the write. Because FW will - // not accept the command. - PlatformIOWrite4Byte(dev, QPNR, Data); - /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware - to finish RF write operation. */ - /* 2008/01/17 MH We support delay in firmware side now. */ - //delay_us(20); -#endif -} /* phy_FwRFSerialWrite */ - -/** -* Function: phy_RFSerialRead -* -* OverView: Read regster from RF chips -* -* Input: -* PADAPTER Adapter, -* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 Offset, //The target address to be read -* -* Output: None -* Return: u32 reback value -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() -*/ -//use in phy only -static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset) -{ - - u32 retValue = 0; - struct r8192_priv *priv = ieee80211_priv(dev); - BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; - u32 NewOffset; - u8 RfPiEnable=0; - - - // - // Make sure RF register offset is correct - // - Offset &= 0x3f; - - // - // Switch page for 8256 RF IC - // - if( priv->rf_chip == RF_8256 || - priv->rf_chip == RF_8225 || - priv->rf_chip == RF_6052) - { - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - - if(Offset>=31) - { - priv->RFReadPageCnt[2]++;//cosa add for debug - priv->RfReg0Value[eRFPath] |= 0x140; - - // Switch to Reg_Mode2 for Reg31~45 - rtl8192_setBBreg(dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - - // Modified Offset - NewOffset = Offset - 30; - - }else if(Offset>=16) - { - priv->RFReadPageCnt[1]++;//cosa add for debug - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - - // Switch to Reg_Mode1 for Reg16~30 - rtl8192_setBBreg(dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - - // Modified Offset - NewOffset = Offset - 15; - } - else - { - priv->RFReadPageCnt[0]++;//cosa add for debug - NewOffset = Offset; - } - } - else - NewOffset = Offset; - - // - // Put desired read address to LSSI control register - // - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); - - // - // Issue a posedge trigger - // - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); - rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); - - // TODO: we should not delay such a long time. Ask help from SD3 - mdelay(1); - - retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); - - // Switch back to Reg_Mode0; - if( priv->rf_chip == RF_8256 || - priv->rf_chip == RF_8225 || - priv->rf_chip == RF_0222D) - { - if (Offset >= 0x10) - { - priv->RfReg0Value[eRFPath] &= 0xebf; - - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - } - - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] - } - - return retValue; -} - - - -/** -* Function: phy_RFSerialWrite -* -* OverView: Write data to RF register (page 8~) -* -* Input: -* PADAPTER Adapter, -* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 Offset, //The target address to be read -* u32 Data //The new register Data in the target bit position -* //of the target to be read -* -* Output: None -* Return: None -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() - * - * Note: For RF8256 only - * The total count of RTL8256(Zebra4) register is around 36 bit it only employs - * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) - * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration - * programming guide" for more details. - * Thus, we define a sub-finction for RTL8526 register address conversion - * =========================================================== - * Register Mode RegCTL[1] RegCTL[0] Note - * (Reg00[12]) (Reg00[10]) - * =========================================================== - * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) - * ------------------------------------------------------------------ -*/ -////use in phy only -static void -phy_RFSerialWrite( - struct net_device* dev, - RF90_RADIO_PATH_E eRFPath, - u32 Offset, - u32 Data - ) -{ - u32 DataAndAddr = 0; - struct r8192_priv *priv = ieee80211_priv(dev); - BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; - u32 NewOffset; - - Offset &= 0x3f; - - // Shadow Update - PHY_RFShadowWrite(dev, eRFPath, Offset, Data); - - - // Switch page for 8256 RF IC - if( priv->rf_chip == RF_8256 || - priv->rf_chip == RF_8225 || - priv->rf_chip == RF_0222D) - { - //analog to digital off, for protection - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] - - if(Offset>=31) - { - priv->RFWritePageCnt[2]++;//cosa add for debug - priv->RfReg0Value[eRFPath] |= 0x140; - - rtl8192_setBBreg(dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - - NewOffset = Offset - 30; - - }else if(Offset>=16) - { - priv->RFWritePageCnt[1]++;//cosa add for debug - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); - - - rtl8192_setBBreg(dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - - NewOffset = Offset - 15; - } - else - { - priv->RFWritePageCnt[0]++;//cosa add for debug - NewOffset = Offset; - } - } - else - NewOffset = Offset; - - // - // Put write addr in [5:0] and write data in [31:16] - // - DataAndAddr = (Data<<16) | (NewOffset&0x3f); - - // - // Write Operation - // - rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); - - - if(Offset==0x0) - priv->RfReg0Value[eRFPath] = Data; - - // Switch back to Reg_Mode0; - if( priv->rf_chip == RF_8256 || - priv->rf_chip == RF_8225 || - priv->rf_chip == RF_0222D) - { - if (Offset >= 0x10) - { - if(Offset != 0) - { - priv->RfReg0Value[eRFPath] &= 0xebf; - rtl8192_setBBreg( - dev, - pPhyReg->rf3wireOffset, - bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16) ); - } - } - //analog to digital on - rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8] - } - -} -#else /** * Function: phy_RFSerialRead * @@ -1276,7 +870,6 @@ phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u3 } #endif -#endif /** * Function: phy_CalculateBitShift @@ -3376,9 +2969,7 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX #endif if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) ) { -#ifdef RTL8192SE - PHY_SetBWModeCallback8192S(dev); -#elif defined(RTL8192SU) +#if defined(RTL8192SU) SetBWModeCallback8192SUsbWorkItem(dev); #endif } @@ -3495,9 +3086,7 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower)) { -#ifdef RTL8192SE - PHY_SwChnlCallback8192S(dev); -#elif defined(RTL8192SU) +#if defined(RTL8192SU) SwChnlCallback8192SUsbWorkItem(dev); #endif #ifdef TO_DO_LIST @@ -3750,7 +3339,7 @@ phy_SwChnlStepByStep( case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) { -#if (defined RTL8192SE ||defined RTL8192SU ) +#if defined RTL8192SU // For new T65 RF 0222d register 0x18 bit 0-9 = channel number. rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2)); //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f)); -- cgit v1.2.3