From 88c1918a71b934844780b217d931485c497fc6b4 Mon Sep 17 00:00:00 2001 From: Andy Green Date: Fri, 30 Jan 2009 09:53:40 +0000 Subject: fix-s3c6410-hsusb-phy-regs.patch Signed-off-by: Andy Green --- drivers/usb/gadget/s3c_hs_otg.c | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'drivers/usb') diff --git a/drivers/usb/gadget/s3c_hs_otg.c b/drivers/usb/gadget/s3c_hs_otg.c index 25c62bd6303..dc7a4f08867 100644 --- a/drivers/usb/gadget/s3c_hs_otg.c +++ b/drivers/usb/gadget/s3c_hs_otg.c @@ -118,17 +118,17 @@ udc_proc_read(char *page, char **start, off_t off, int count, static u32 s3c_otg_readl(struct s3c_udc *dev, u32 reg) { - return readl((u32)dev->reg_base + reg); + return __raw_readl((u32)dev->reg_base + reg); } -static inline void s3c_otg_writel(struct s3c_udc *dev, u32 val, u32 reg, int update) +static void s3c_otg_writel(struct s3c_udc *dev, u32 val, u32 reg, int update) { u32 temp = 0; if (update) - temp = readl(((u32)dev->reg_base) + reg); + temp = __raw_readl(((u32)dev->reg_base) + reg); - writel(val|temp, ((u32)dev->reg_base) + reg); + __raw_writel(val|temp, ((u32)dev->reg_base) + reg); } /* @@ -900,7 +900,7 @@ void s3c_otg_set_ep(struct s3c_udc *dev, enum usb_device_speed speed) */ static void s3c_otg_set_address(struct s3c_udc *dev, unsigned char addr) { - s3c_otg_writel(dev, DEVICE_ADDR(addr), (u32)S3C_UDC_OTG_DCFG, 1); + s3c_otg_writel(dev, DEVICE_ADDR(addr), S3C_UDC_OTG_DCFG, 1); s3c_otg_ep_control(0, USB_DIR_IN, DEPCTL_EPENA|DEPCTL_CNAK, 1); DBG(2, "USB OTG 2.0 Device Address=%d\n", addr); @@ -1085,7 +1085,7 @@ static void s3c_otg_handle_ep(struct s3c_udc *dev, u32 gintmsk) u32 bytes = 0; gintmsk &= ~INT_RX_FIFO_NOT_EMPTY; - s3c_otg_writel(dev, gintmsk, (u32)S3C_UDC_OTG_GINTMSK, 0); + s3c_otg_writel(dev, gintmsk, S3C_UDC_OTG_GINTMSK, 0); csr = s3c_otg_readl(dev, S3C_UDC_OTG_GRXSTSR); @@ -1146,7 +1146,7 @@ static void s3c_otg_handle_ep(struct s3c_udc *dev, u32 gintmsk) gintmsk |= INT_RX_FIFO_NOT_EMPTY; } - s3c_otg_writel(dev, gintmsk, (u32)S3C_UDC_OTG_GINTMSK, 0); + s3c_otg_writel(dev, gintmsk, S3C_UDC_OTG_GINTMSK, 0); } /* @@ -1160,7 +1160,7 @@ static void s3c_otg_disable(struct s3c_udc *dev) dev->gadget.speed = USB_SPEED_UNKNOWN; dev->usb_address = 0; - s3c_otg_writel(dev, ANALOG_PWR_DOWN, (u32)S3C_USBOTG_PHYPWR, 1); + s3c_otg_writel(dev, ANALOG_PWR_DOWN, S3C_USBOTG_PHYPWR, 1); } /* @@ -1208,27 +1208,27 @@ static void s3c_otg_config(struct s3c_udc *dev) u32 reg; /* OTG USB configuration */ - s3c_otg_writel(dev, GUSBCFG_INIT, (u32)S3C_UDC_OTG_GUSBCFG, 0); + s3c_otg_writel(dev, GUSBCFG_INIT, S3C_UDC_OTG_GUSBCFG, 0); /* Soft-reset OTG Core and then unreset again */ - s3c_otg_writel(dev, CORE_SOFT_RESET, (u32)S3C_UDC_OTG_GRSTCTL, 0); + s3c_otg_writel(dev, CORE_SOFT_RESET, S3C_UDC_OTG_GRSTCTL, 0); /* Put the OTG device core in the disconnected state */ - s3c_otg_writel(dev, SOFT_DISCONNECT, (u32)S3C_UDC_OTG_DCTL, 1); + s3c_otg_writel(dev, SOFT_DISCONNECT, S3C_UDC_OTG_DCTL, 1); udelay(20); /* Make the OTG device core exit from the disconnected state */ reg = s3c_otg_readl(dev, S3C_UDC_OTG_DCTL); - s3c_otg_writel(dev, reg & ~SOFT_DISCONNECT, (u32)S3C_UDC_OTG_DCTL, 0); + s3c_otg_writel(dev, reg & ~SOFT_DISCONNECT, S3C_UDC_OTG_DCTL, 0); /* Configure OTG Core to initial settings of device mode */ - s3c_otg_writel(dev, EP_MIS_CNT(0x1)|SPEED_2_HIGH, (u32)S3C_UDC_OTG_DCFG, 1); + s3c_otg_writel(dev, EP_MIS_CNT(0x1)|SPEED_2_HIGH, S3C_UDC_OTG_DCFG, 0 /*1*/); udelay(1000); /* Unmask the core interrupts */ - s3c_otg_writel(dev, GINTMSK_INIT, (u32)S3C_UDC_OTG_GINTMSK, 0); + s3c_otg_writel(dev, GINTMSK_INIT, S3C_UDC_OTG_GINTMSK, 0); /* Set NAK bit of EP0, EP1, EP2 */ s3c_otg_ep_control(0, USB_DIR_OUT, @@ -1251,13 +1251,13 @@ static void s3c_otg_config(struct s3c_udc *dev) (u32)S3C_UDC_OTG_DAINTMSK, 0); /* Unmask device OUT EP common interrupts */ - s3c_otg_writel(dev, DOEPMSK_INIT, (u32)S3C_UDC_OTG_DOEPMSK, 0); + s3c_otg_writel(dev, DOEPMSK_INIT, S3C_UDC_OTG_DOEPMSK, 0); /* Unmask device IN EP common interrupts */ - s3c_otg_writel(dev, DIEPMSK_INIT, (u32)S3C_UDC_OTG_DIEPMSK, 0); + s3c_otg_writel(dev, DIEPMSK_INIT, S3C_UDC_OTG_DIEPMSK, 0); /* Set Rx FIFO Size */ - s3c_otg_writel(dev, RX_FIFO_SIZE, (u32)S3C_UDC_OTG_GRXFSIZ, 0); + s3c_otg_writel(dev, RX_FIFO_SIZE, S3C_UDC_OTG_GRXFSIZ, 0); /* Set Non Periodic Tx FIFO Size */ s3c_otg_writel(dev, NPTX_FIFO_SIZE|NPTX_FIFO_START_ADDR, @@ -1267,7 +1267,7 @@ static void s3c_otg_config(struct s3c_udc *dev) s3c_otg_ep_control(0, USB_DIR_OUT, DEPCTL_EPDIS|DEPCTL_CNAK, 0); /* Initialize OTG Link Core */ - s3c_otg_writel(dev, GAHBCFG_INIT, (u32)S3C_UDC_OTG_GAHBCFG, 0); + s3c_otg_writel(dev, GAHBCFG_INIT, S3C_UDC_OTG_GAHBCFG, 0); } static int s3c_otg_enable(struct s3c_udc *dev) @@ -1277,14 +1277,14 @@ static int s3c_otg_enable(struct s3c_udc *dev) S3C64XX_OTHERS); /* Initializes OTG Phy. */ - s3c_otg_writel(dev, SUSPEND_DISABLE, (u32)S3C_USBOTG_PHYPWR, 0); + s3c_otg_writel(dev, SUSPEND_DISABLE, S3C_USBOTG_PHYPWR, 0); - s3c_otg_writel(dev, dev->phyclk, (u32)S3C_USBOTG_PHYCLK, 0); + s3c_otg_writel(dev, dev->phyclk, S3C_USBOTG_PHYCLK, 0); - s3c_otg_writel(dev, SW_RST_ON, (u32)S3C_USBOTG_RSTCON, 0); + s3c_otg_writel(dev, SW_RST_ON, S3C_USBOTG_RSTCON, 0); udelay(50); - s3c_otg_writel(dev, SW_RST_OFF, (u32)S3C_USBOTG_RSTCON, 0); + s3c_otg_writel(dev, SW_RST_OFF, S3C_USBOTG_RSTCON, 0); udelay(50); s3c_otg_config(dev); @@ -1333,12 +1333,12 @@ static irqreturn_t s3c_otg_irq(int irq, void *_dev) if (intr_status & INT_EARLY_SUSPEND) { DBG(2, "Early suspend interrupt\n"); - s3c_otg_writel(dev, INT_EARLY_SUSPEND, (u32)S3C_UDC_OTG_GINTSTS, 0); + s3c_otg_writel(dev, INT_EARLY_SUSPEND, S3C_UDC_OTG_GINTSTS, 0); } if (intr_status & INT_SUSPEND) { DBG(2, "Suspend interrupt\n"); - s3c_otg_writel(dev, INT_SUSPEND, (u32)S3C_UDC_OTG_GINTSTS, 0); + s3c_otg_writel(dev, INT_SUSPEND, S3C_UDC_OTG_GINTSTS, 0); if (dev->gadget.speed != USB_SPEED_UNKNOWN && dev->driver @@ -1349,7 +1349,7 @@ static irqreturn_t s3c_otg_irq(int irq, void *_dev) if (intr_status & INT_RESUME) { DBG(2, "Resume interrupt\n"); - s3c_otg_writel(dev, INT_RESUME, (u32)S3C_UDC_OTG_GINTSTS, 0); + s3c_otg_writel(dev, INT_RESUME, S3C_UDC_OTG_GINTSTS, 0); if (dev->gadget.speed != USB_SPEED_UNKNOWN && dev->driver @@ -1360,7 +1360,7 @@ static irqreturn_t s3c_otg_irq(int irq, void *_dev) if (intr_status & INT_RESET) { DBG(2, "Reset interrupt\n"); - s3c_otg_writel(dev, INT_RESET, (u32)S3C_UDC_OTG_GINTSTS, 0); + s3c_otg_writel(dev, INT_RESET, S3C_UDC_OTG_GINTSTS, 0); usb_status = s3c_otg_readl(dev, S3C_UDC_OTG_GOTGCTL); -- cgit v1.2.3