From a1ee06b72968d80ab9362ec61143c4f090cc2d1b Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Thu, 21 Jan 2010 18:55:32 +0100 Subject: i2c: mxc: let time to generate stop bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After generating the stop bit by changing MSTA from 1 to 0, the i2c_imx->stopped was immediatly set to 1. The second test on i2c_imx->stopped then is correct and the controller never waits if the bus is busy. This patch corrects this. On mx31moboard, stop bit was not generated on single write transfers. This was kept unnoticed as other transfers are made afterwards that help the write recipient to resynchronize. Thanks to Philippe and Michael for the debugging. Signed-off-by: Valentin Longchamp Signed-off by: Philippe Rétornaz Reported-by: Michael Bonani Acked-by; Wolfram Sang Signed-off-by: Ben Dooks --- drivers/i2c/busses/i2c-imx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index e3654d683e1..602b30e32cf 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -226,7 +226,6 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) temp = readb(i2c_imx->base + IMX_I2C_I2CR); temp &= ~(I2CR_MSTA | I2CR_MTX); writeb(temp, i2c_imx->base + IMX_I2C_I2CR); - i2c_imx->stopped = 1; } if (cpu_is_mx1()) { /* @@ -236,8 +235,10 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) udelay(i2c_imx->disable_delay); } - if (!i2c_imx->stopped) + if (!i2c_imx->stopped) { i2c_imx_bus_busy(i2c_imx, 0); + i2c_imx->stopped = 1; + } /* Disable I2C controller */ writeb(0, i2c_imx->base + IMX_I2C_I2CR); -- cgit v1.2.3