From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- include/asm-arm/arch-epxa10db/mode_ctrl00.h | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 include/asm-arm/arch-epxa10db/mode_ctrl00.h (limited to 'include/asm-arm/arch-epxa10db/mode_ctrl00.h') diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h new file mode 100644 index 00000000000..d8a7efa12e1 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/mode_ctrl00.h @@ -0,0 +1,80 @@ +#ifndef __MODE_CTRL00_H +#define __MODE_CTRL00_H + +/* + * Register definitions for the reset and mode control + */ + +/* + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + + +#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR )) +#define BOOT_CR_BF_MSK (0x1) +#define BOOT_CR_BF_OFST (0) +#define BOOT_CR_HM_MSK (0x2) +#define BOOT_CR_HM_OFST (1) +#define BOOT_CR_RE_MSK (0x4) +#define BOOT_CR_RE_OFST (2) + +#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 )) +#define RESET_SR_WR_MSK (0x1) +#define RESET_SR_WR_OFST (0) +#define RESET_SR_CR_MSK (0x2) +#define RESET_SR_CR_OFST (1) +#define RESET_SR_JT_MSK (0x4) +#define RESET_SR_JT_OFST (2) +#define RESET_SR_ER_MSK (0x8) +#define RESET_SR_ER_OFST (3) + +#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 )) + +#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 )) +#define SRAM0_SR_SIZE_MSK (0xFFFFF000) +#define SRAM0_SR_SIZE_OFST (12) + +#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 )) +#define SRAM1_SR_SIZE_MSK (0xFFFFF000) +#define SRAM1_SR_SIZE_OFST (12) + +#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 )) + +#define DPSRAM0_SR_MODE_MSK (0xF) +#define DPSRAM0_SR_MODE_OFST (0) +#define DPSRAM0_SR_GLBL_MSK (0x30) +#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000) +#define DPSRAM0_SR_SIZE_OFST (12) + +#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 )) +#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0) +#define DPSRAM0_LCR_LCKADDR_OFST (4) + +#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 )) +#define DPSRAM1_SR_MODE_MSK (0xF) +#define DPSRAM1_SR_MODE_OFST (0) +#define DPSRAM1_SR_GLBL_MSK (0x30) +#define DPSRAM1_SR_GLBL_OFST (4) +#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000) +#define DPSRAM1_SR_SIZE_OFST (12) + +#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C )) +#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0) +#define DPSRAM1_LCR_LCKADDR_OFST (4) + +#endif /* __MODE_CTRL00_H */ -- cgit v1.2.3