From 7ad1bcb25c5623f1f87c50fdf2272f58ff91db5a Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 27 Aug 2006 12:07:02 +0100 Subject: [ARM] Add ARM irqtrace support This adds support for irqtrace for lockdep on ARM. Signed-off-by: Russell King --- include/asm-arm/system.h | 125 +---------------------------------------------- 1 file changed, 1 insertion(+), 124 deletions(-) (limited to 'include/asm-arm/system.h') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 0947cbf9b69..174ff52661b 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -207,130 +207,7 @@ static inline void sched_cacheflush(void) { } -/* - * CPU interrupt mask handling. - */ -#if __LINUX_ARM_ARCH__ >= 6 - -#define local_irq_save(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ - "cpsid i" \ - : "=r" (x) : : "memory", "cc"); \ - }) - -#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") -#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") -#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") -#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") - -#else - -/* - * Save the current interrupt enable state & disable IRQs - */ -#define local_irq_save(x) \ - ({ \ - unsigned long temp; \ - (void) (&temp == &x); \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ -" orr %1, %0, #128\n" \ -" msr cpsr_c, %1" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Enable IRQs - */ -#define local_irq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_enable\n" \ -" bic %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Disable IRQs - */ -#define local_irq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_disable\n" \ -" orr %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Enable FIQs - */ -#define local_fiq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ stf\n" \ -" bic %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -/* - * Disable FIQs - */ -#define local_fiq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ clf\n" \ -" orr %0, %0, #64\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - -#endif - -/* - * Save the current interrupt enable state. - */ -#define local_save_flags(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_save_flags" \ - : "=r" (x) : : "memory", "cc"); \ - }) - -/* - * restore saved IRQ & FIQ state - */ -#define local_irq_restore(x) \ - __asm__ __volatile__( \ - "msr cpsr_c, %0 @ local_irq_restore\n" \ - : \ - : "r" (x) \ - : "memory", "cc") - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - (int)(flags & PSR_I_BIT); \ -}) +#include #ifdef CONFIG_SMP -- cgit v1.2.3 From e7cc2c59cc83558fc26f17eee3c8f901119f0a7c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 03:35:20 +0100 Subject: [ARM] 3852/1: convert atomic bitops and __xchg over to raw_local_irq_{save,restore} Thomas Gleixner noticed that bitops.h should also use the raw_* irq disable/enable variants, and __xchg needs them as well. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/system.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/asm-arm/system.h') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 174ff52661b..c19c5b009f7 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -282,17 +282,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size #error SMP is not supported on this platform #endif case 1: - local_irq_save(flags); + raw_local_irq_save(flags); ret = *(volatile unsigned char *)ptr; *(volatile unsigned char *)ptr = x; - local_irq_restore(flags); + raw_local_irq_restore(flags); break; case 4: - local_irq_save(flags); + raw_local_irq_save(flags); ret = *(volatile unsigned long *)ptr; *(volatile unsigned long *)ptr = x; - local_irq_restore(flags); + raw_local_irq_restore(flags); break; #else case 1: -- cgit v1.2.3 From f12d0d7c7786af39435ef6ae9defe47fb58f6091 Mon Sep 17 00:00:00 2001 From: "Hyok S. Choi" Date: Tue, 26 Sep 2006 17:36:37 +0900 Subject: [ARM] nommu: manage the CP15 things All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi Signed-off-by: Russell King --- include/asm-arm/system.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm/system.h') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index c19c5b009f7..f05fbe31576 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -46,6 +46,7 @@ #define CPUID_TCM 2 #define CPUID_TLBTYPE 3 +#ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ unsigned int __val; \ @@ -55,6 +56,9 @@ : "cc"); \ __val; \ }) +#else +#define read_cpuid(reg) (processor_id) +#endif /* * This is used to ensure the compiler did actually allocate the register we -- cgit v1.2.3