From 7bbb3cc5c816fc167601ce9519adae5eced3ea6d Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 6 Dec 2006 17:13:54 -0800 Subject: ARM: OMAP: 24xx pinmux updates Add some OMAP 24xx pin mux declarations to support: - TUSB 6010 EVM (on H4) - All three full speed USB ports - GPIOs used with USB0 on Apollon and H4 For OMAP2, issue MUX_WARNINGS and debug messages correctly; and make the message look more like the OMAP1 message. Signed-off-by: Kyungmin Park Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/mux.h | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 828cc5c114e..f1ec2edd404 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -421,7 +421,9 @@ enum omap24xx_index { /* 24xx clock */ W14_24XX_SYS_CLKOUT, - /* 24xx GPMC wait pin monitoring */ + /* 24xx GPMC chipselects, wait pin monitoring */ + E2_GPMC_NCS2, + L2_GPMC_NCS7, L3_GPMC_WAIT0, N7_GPMC_WAIT1, M1_GPMC_WAIT2, @@ -435,6 +437,7 @@ enum omap24xx_index { /* 24xx GPIO */ M21_242X_GPIO11, + P21_242X_GPIO12, AA10_242X_GPIO13, AA6_242X_GPIO14, AA4_242X_GPIO15, @@ -444,7 +447,9 @@ enum omap24xx_index { Y20_24XX_GPIO60, W4__24XX_GPIO74, M15_24XX_GPIO92, + J15_24XX_GPIO99, V14_24XX_GPIO117, + P14_24XX_GPIO125, /* 242x DBG GPIO */ V4_242X_GPIO49, @@ -486,6 +491,30 @@ enum omap24xx_index { G18_24XX_MMC_CMD_DIR, H15_24XX_MMC_CLKI, + /* Full speed USB */ + J20_24XX_USB0_PUEN, + J19_24XX_USB0_VP, + K20_24XX_USB0_VM, + J18_24XX_USB0_RCV, + K19_24XX_USB0_TXEN, + J14_24XX_USB0_SE0, + K18_24XX_USB0_DAT, + + N14_24XX_USB1_SE0, + W12_24XX_USB1_SE0, + P15_24XX_USB1_DAT, + R13_24XX_USB1_DAT, + W20_24XX_USB1_TXEN, + P13_24XX_USB1_TXEN, + V19_24XX_USB1_RCV, + V12_24XX_USB1_RCV, + + AA10_24XX_USB2_SE0, + Y11_24XX_USB2_DAT, + AA12_24XX_USB2_TXEN, + AA6_24XX_USB2_RCV, + AA4_24XX_USB2_TLLSE0, + /* Keypad GPIO*/ T19_24XX_KBR0, R19_24XX_KBR1, -- cgit v1.2.3 From c7b87f3d5037a35b5c7bb916ffc826be3fcb208d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 16:46:13 +0100 Subject: [ARM] ecard: add helper function for setting ecard irq ops Rather than having every driver fiddle about setting its private IRQ operations and data, provide a helper function to contain this functionality in one place. Arrange to remove the driver-private IRQ operations and data when the device is removed from the driver, and remove the driver private code to do this. This fixes potential problems caused by drivers forgetting to remove these hooks. Signed-off-by: Russell King --- include/asm-arm/ecard.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 3a6d3eb2762..8f1000eac91 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -121,7 +121,7 @@ struct in_ecid { /* Packed card ID information */ typedef struct expansion_card ecard_t; typedef unsigned long *loader_t; -typedef struct { /* Card handler routines */ +typedef struct expansion_card_ops { /* Card handler routines */ void (*irqenable)(ecard_t *ec, int irqnr); void (*irqdisable)(ecard_t *ec, int irqnr); int (*irqpending)(ecard_t *ec); @@ -179,6 +179,8 @@ struct expansion_card { u64 dma_mask; }; +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); + struct in_chunk_dir { unsigned int start_offset; union { -- cgit v1.2.3 From 10bdaaa0fad620145cf10e2b573266b2d80b44de Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 18:40:51 +0100 Subject: [ARM] ecard: add ecardm_iomap() / ecardm_iounmap() Add devres ecardm_iomap() and ecardm_iounmap() for Acorn expansion cards. Convert all expansion card drivers to use them. Signed-off-by: Russell King --- include/asm-arm/ecard.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 8f1000eac91..684fe064523 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -226,6 +226,10 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) extern int ecard_request_resources(struct expansion_card *ec); extern void ecard_release_resources(struct expansion_card *ec); +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize); +#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) + extern struct bus_type ecard_bus_type; #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) -- cgit v1.2.3 From b8b6970b4fe08397554295b0c5169bec7575f7c9 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Wed, 9 May 2007 15:55:24 +0100 Subject: [ARM] 4365/1: Add AC97 clock to s3c2443 machine This adds the ac97 clock to the s3c2443 machine files. It seems to have been simply missed out previously. Signed-off-by: Graeme Gregory Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index cd9e26568f8..c1414658d1c 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h @@ -129,6 +129,7 @@ #define S3C2443_PCLKCON_IIC (1<<4) #define S3C2443_PCLKCON_SDI (1<<5) #define S3C2443_PCLKCON_ADC (1<<7) +#define S3C2443_PCLKCON_AC97 (1<<8) #define S3C2443_PCLKCON_IIS (1<<9) #define S3C2443_PCLKCON_PWMT (1<<10) #define S3C2443_PCLKCON_WDT (1<<11) -- cgit v1.2.3 From f75fd965d500d33720948f30d409c6c7729a80af Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 9 May 2007 20:21:11 +0100 Subject: [ARM] Fix iop32x/iop33x build arch/arm/plat-iop/io.c:26: error: conflicting types for '__iop3xx_ioremap' Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/io.h | 2 +- include/asm-arm/arch-iop32x/io.h | 2 +- include/asm-arm/arch-iop33x/io.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4ad82b..a6e0f9e6ddc 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h @@ -27,7 +27,7 @@ extern void __iomem * __iop13xx_io(unsigned long io_addr); extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop13xx_iounmap(void __iomem *addr); extern u32 iop13xx_atue_mem_base; diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16af505..958af751a48 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f7589b29..fec9c53e2b1 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff -- cgit v1.2.3 From 030f4810e782e541468d36c27e721b582b7820a4 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 13:21:27 +0100 Subject: [ARM] 4369/1: AT91: Fix circular dependency in header files Resolve the circular dependency in the AT91 header files (io.h and hardware.h) by moving the at91_sys_read() and at91_sys_write() functions to io.h Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/hardware.h | 17 ----------------- include/asm-arm/arch-at91/io.h | 18 ++++++++++++++++++ include/asm-arm/arch-at91/irqs.h | 1 + include/asm-arm/arch-at91/uncompress.h | 2 +- 4 files changed, 20 insertions(+), 18 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154d..1c14382dc3f 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -69,22 +69,5 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -#ifndef __ASSEMBLY__ -#include - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif #endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327ec04..80073fd36b8 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -29,4 +29,22 @@ #define __mem_pci(a) (a) +#ifndef __ASSEMBLY__ + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif + #endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb9a9c..1127a3b5e92 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -21,6 +21,7 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H +#include #include #define NR_AIC_IRQS 32 diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28304b..30ac587b3b4 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include +#include #include /* -- cgit v1.2.3 From 7c6337e225364870e9bf02a3ae277d9fdea483f8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 30 Apr 2007 19:37:19 +0100 Subject: [ARM] 4303/3: base kernel support for TI DaVinci Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: Kevin Hilman Signed-off-by: Russell King --- include/asm-arm/arch-davinci/common.h | 19 ++++++ include/asm-arm/arch-davinci/debug-macro.S | 21 ++++++ include/asm-arm/arch-davinci/dma.h | 16 +++++ include/asm-arm/arch-davinci/entry-macro.S | 32 +++++++++ include/asm-arm/arch-davinci/hardware.h | 14 ++++ include/asm-arm/arch-davinci/io.h | 79 ++++++++++++++++++++++ include/asm-arm/arch-davinci/irqs.h | 105 +++++++++++++++++++++++++++++ include/asm-arm/arch-davinci/memory.h | 64 ++++++++++++++++++ include/asm-arm/arch-davinci/psc.h | 76 +++++++++++++++++++++ include/asm-arm/arch-davinci/serial.h | 20 ++++++ include/asm-arm/arch-davinci/system.h | 29 ++++++++ include/asm-arm/arch-davinci/timex.h | 17 +++++ include/asm-arm/arch-davinci/uncompress.h | 35 ++++++++++ include/asm-arm/arch-davinci/vmalloc.h | 15 +++++ 14 files changed, 542 insertions(+) create mode 100644 include/asm-arm/arch-davinci/common.h create mode 100644 include/asm-arm/arch-davinci/debug-macro.S create mode 100644 include/asm-arm/arch-davinci/dma.h create mode 100644 include/asm-arm/arch-davinci/entry-macro.S create mode 100644 include/asm-arm/arch-davinci/hardware.h create mode 100644 include/asm-arm/arch-davinci/io.h create mode 100644 include/asm-arm/arch-davinci/irqs.h create mode 100644 include/asm-arm/arch-davinci/memory.h create mode 100644 include/asm-arm/arch-davinci/psc.h create mode 100644 include/asm-arm/arch-davinci/serial.h create mode 100644 include/asm-arm/arch-davinci/system.h create mode 100644 include/asm-arm/arch-davinci/timex.h create mode 100644 include/asm-arm/arch-davinci/uncompress.h create mode 100644 include/asm-arm/arch-davinci/vmalloc.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h new file mode 100644 index 00000000000..a97dfbb15e5 --- /dev/null +++ b/include/asm-arm/arch-davinci/common.h @@ -0,0 +1,19 @@ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +struct sys_timer; + +extern struct sys_timer davinci_timer; + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S new file mode 100644 index 00000000000..e6c0f0d5d06 --- /dev/null +++ b/include/asm-arm/arch-davinci/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro for DaVinci + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x01000000 @ physical base address + movne \rx, #0xfe000000 @ virtual base + orr \rx, \rx, #0x00c20000 @ UART 0 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h new file mode 100644 index 00000000000..8e2f2d0ba66 --- /dev/null +++ b/include/asm-arm/arch-davinci/dma.h @@ -0,0 +1,16 @@ +/* + * DaVinci DMA definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S new file mode 100644 index 00000000000..3ebfcc5cb58 --- /dev/null +++ b/include/asm-arm/arch-davinci/entry-macro.S @@ -0,0 +1,32 @@ +/* + * Low-level IRQ helper macros for TI DaVinci-based platforms + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \tmp, [\base, #0x14] + mov \tmp, \tmp, lsr #2 + sub \irqnr, \tmp, #1 + cmp \tmp, #0 + .endm + + .macro irq_prio_table + .endm diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 00000000000..60362d80229 --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,14 @@ +/* + * Common hardware definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 00000000000..e7accb91086 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h @@ -0,0 +1,79 @@ +/* + * DaVinci IO address definitions + * + * Copied from include/asm/arm/arch-omap/io.h + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_p2v(pa) ((pa) + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define IO_ADDRESS(x) io_p2v(x) + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define PCIO_BASE 0 +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#ifndef __ASSEMBLER__ + +/* + * Functions to access the DaVinci IO region + * + * NOTE: - Use davinci_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) + +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) + +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] + +#define __REG(paddr) __REGV32(io_p2v(paddr)) +#else + +#define __REG(x) (*((volatile unsigned long *)io_p2v(x))) + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_ARCH_IO_H */ diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h new file mode 100644 index 00000000000..f4c5ca6da9f --- /dev/null +++ b/include/asm-arm/arch-davinci/irqs.h @@ -0,0 +1,105 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* Base address */ +#define DAVINCI_ARM_INTC_BASE 0x01C48000 + +/* Interrupt lines */ +#define IRQ_VDINT0 0 +#define IRQ_VDINT1 1 +#define IRQ_VDINT2 2 +#define IRQ_HISTINT 3 +#define IRQ_H3AINT 4 +#define IRQ_PRVUINT 5 +#define IRQ_RSZINT 6 +#define IRQ_VFOCINT 7 +#define IRQ_VENCINT 8 +#define IRQ_ASQINT 9 +#define IRQ_IMXINT 10 +#define IRQ_VLCDINT 11 +#define IRQ_USBINT 12 +#define IRQ_EMACINT 13 + +#define IRQ_CCINT0 16 +#define IRQ_CCERRINT 17 +#define IRQ_TCERRINT0 18 +#define IRQ_TCERRINT 19 +#define IRQ_PSCIN 20 + +#define IRQ_IDE 22 +#define IRQ_HPIINT 23 +#define IRQ_MBXINT 24 +#define IRQ_MBRINT 25 +#define IRQ_MMCINT 26 +#define IRQ_SDIOINT 27 +#define IRQ_MSINT 28 +#define IRQ_DDRINT 29 +#define IRQ_AEMIFINT 30 +#define IRQ_VLQINT 31 +#define IRQ_TINT0_TINT12 32 +#define IRQ_TINT0_TINT34 33 +#define IRQ_TINT1_TINT12 34 +#define IRQ_TINT1_TINT34 35 +#define IRQ_PWMINT0 36 +#define IRQ_PWMINT1 37 +#define IRQ_PWMINT2 38 +#define IRQ_I2C 39 +#define IRQ_UARTINT0 40 +#define IRQ_UARTINT1 41 +#define IRQ_UARTINT2 42 +#define IRQ_SPINT0 43 +#define IRQ_SPINT1 44 + +#define IRQ_DSP2ARM0 46 +#define IRQ_DSP2ARM1 47 +#define IRQ_GPIO0 48 +#define IRQ_GPIO1 49 +#define IRQ_GPIO2 50 +#define IRQ_GPIO3 51 +#define IRQ_GPIO4 52 +#define IRQ_GPIO5 53 +#define IRQ_GPIO6 54 +#define IRQ_GPIO7 55 +#define IRQ_GPIOBNK0 56 +#define IRQ_GPIOBNK1 57 +#define IRQ_GPIOBNK2 58 +#define IRQ_GPIOBNK3 59 +#define IRQ_GPIOBNK4 60 +#define IRQ_COMMTX 61 +#define IRQ_COMMRX 62 +#define IRQ_EMUINT 63 + +#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_GPIO 71 + +#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) + +#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h new file mode 100644 index 00000000000..dd1625c23cf --- /dev/null +++ b/include/asm-arm/arch-davinci/memory.h @@ -0,0 +1,64 @@ +/* + * DaVinci memory space definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/************************************************************************** + * Included Files + **************************************************************************/ +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ +#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ + +#define PHYS_OFFSET DAVINCI_DDR_BASE + +/* + * Increase size of DMA-consistent memory region + */ +#define CONSISTENT_DMA_SIZE (14<<20) + +#ifndef __ASSEMBLY__ +/* + * Restrict DMA-able region to workaround silicon bug. The bug + * restricts buffers available for DMA to video hardware to be + * below 128M + */ +static inline void +__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) +{ + unsigned int sz = (128<<20) >> PAGE_SHIFT; + + if (node != 0) + sz = 0; + + size[1] = size[0] - sz; + size[0] = sz; +} + +#define arch_adjust_zones(node, zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) + +#endif + +/* + * Bus address is physical address + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h new file mode 100644 index 00000000000..4977aa071e1 --- /dev/null +++ b/include/asm-arm/arch-davinci/psc.h @@ -0,0 +1,76 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h new file mode 100644 index 00000000000..ed418ef7680 --- /dev/null +++ b/include/asm-arm/arch-davinci/serial.h @@ -0,0 +1,20 @@ +/* + * DaVinci serial device definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include + +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h new file mode 100644 index 00000000000..440ac515804 --- /dev/null +++ b/include/asm-arm/arch-davinci/system.h @@ -0,0 +1,29 @@ +/* + * DaVinci system defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +extern void davinci_watchdog_reset(void); + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static void arch_reset(char mode) +{ + davinci_watchdog_reset(); +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h new file mode 100644 index 00000000000..52827567841 --- /dev/null +++ b/include/asm-arm/arch-davinci/timex.h @@ -0,0 +1,17 @@ +/* + * DaVinci timer defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* The source frequency for the timers is the 27MHz clock */ +#define CLOCK_TICK_RATE 27000000 + +#endif /* __ASM_ARCH_TIMEX_H__ */ diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h new file mode 100644 index 00000000000..f6d1570f720 --- /dev/null +++ b/include/asm-arm/arch-davinci/uncompress.h @@ -0,0 +1,35 @@ +/* + * Serial port stubs for kernel decompress status messages + * + * Author: Anant Gole + * (C) Copyright (C) 2006, Texas Instruments, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include + +/* PORT_16C550A, in polled non-fifo mode */ + +static void putc(char c) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); + uart[UART_TX] = c; +} + +static inline void flush(void) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h new file mode 100644 index 00000000000..9b47fa89b33 --- /dev/null +++ b/include/asm-arm/arch-davinci/vmalloc.h @@ -0,0 +1,15 @@ +/* + * DaVinci vmalloc definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + +/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ +#define VMALLOC_END (IO_VIRT - (2<<20)) -- cgit v1.2.3 From 2fd0237538480c8d704c385b6f9abc3f6c46b760 Mon Sep 17 00:00:00 2001 From: Daniel Wolstenholme Date: Thu, 10 May 2007 22:33:02 -0700 Subject: [ARM] iop13xx: msi support Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [ebiederm@xmission.com: review comments/suggestions] [dan.j.williams@intel.com: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme Signed-off-by: Dan Williams Acked-by: Eric W. Biederman Signed-off-by: Andrew Morton Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/iop13xx.h | 29 +++++++++++++++++++++++++++++ include/asm-arm/arch-iop13xx/irqs.h | 8 +++++++- include/asm-arm/arch-iop13xx/msi.h | 11 +++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 include/asm-arm/arch-iop13xx/msi.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c332..e6736c3d1f7 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_MU_PMMR_OFFSET 0x00004000 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) @@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) /*=======================================================================*/ +/*============================MESSAGING UNIT=============================*/ +#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) +#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) +#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) +#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) +#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) +#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) +#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) +#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) +#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) +#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) +#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) +#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) +#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) +#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) +#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) +#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) + +#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) +#define IOP13XX_MU_BASE_PHYS (0xff000000) +#define IOP13XX_MU_BASE_PCI (0xff000000) +#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) +#define IOP13XX_MU_MIMR_CORE_SELECT (15) +/*=======================================================================*/ + /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 5c6fac2a400..054e7acb5bf 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ +#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ @@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ #define IRQ_IOP13XX_HPI (127) /* 31 */ +#ifdef CONFIG_PCI_MSI +#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) +#else #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#endif + #define NR_IRQS NR_IOP13XX_IRQS #endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h new file mode 100644 index 00000000000..b80c5ae17e9 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/msi.h @@ -0,0 +1,11 @@ +#ifndef _IOP13XX_MSI_H_ +#define _IOP13XX_MSI_H_ +#ifdef CONFIG_PCI_MSI +void iop13xx_msi_init(void); +#else +static inline void iop13xx_msi_init(void) +{ + return; +} +#endif +#endif -- cgit v1.2.3 From 877d7720f5f67793b9b6027840d2c88ea25dc4c8 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 20:49:56 +0100 Subject: [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors. Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: Nicolas Ferre Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91sam9rl.h | 110 ++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91sam9rl_matrix.h | 96 ++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 9 +++ include/asm-arm/arch-at91/hardware.h | 2 + include/asm-arm/arch-at91/timex.h | 5 ++ 5 files changed, 222 insertions(+) create mode 100644 include/asm-arm/arch-at91/at91sam9rl.h create mode 100644 include/asm-arm/arch-at91/at91sam9rl_matrix.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h new file mode 100644 index 00000000000..8a9708a370c --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -0,0 +1,110 @@ +/* + * include/asm-arm/arch-at91/at91sam9260.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Common definitions. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_H +#define AT91SAM9RL_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller */ +#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91SAM9RL_ID_US0 6 /* USART 0 */ +#define AT91SAM9RL_ID_US1 7 /* USART 1 */ +#define AT91SAM9RL_ID_US2 8 /* USART 2 */ +#define AT91SAM9RL_ID_US3 9 /* USART 3 */ +#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ +#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ +#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ +#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ +#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ +#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ +#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ +#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9RL_BASE_TCB0 0xfffa0000 +#define AT91SAM9RL_BASE_TC0 0xfffa0000 +#define AT91SAM9RL_BASE_TC1 0xfffa0040 +#define AT91SAM9RL_BASE_TC2 0xfffa0080 +#define AT91SAM9RL_BASE_MCI 0xfffa4000 +#define AT91SAM9RL_BASE_TWI0 0xfffa8000 +#define AT91SAM9RL_BASE_TWI1 0xfffac000 +#define AT91SAM9RL_BASE_US0 0xfffb0000 +#define AT91SAM9RL_BASE_US1 0xfffb4000 +#define AT91SAM9RL_BASE_US2 0xfffb8000 +#define AT91SAM9RL_BASE_US3 0xfffbc000 +#define AT91SAM9RL_BASE_SSC0 0xfffc0000 +#define AT91SAM9RL_BASE_SSC1 0xfffc4000 +#define AT91SAM9RL_BASE_PWMC 0xfffc8000 +#define AT91SAM9RL_BASE_SPI 0xfffcc000 +#define AT91SAM9RL_BASE_TSC 0xfffd0000 +#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 +#define AT91SAM9RL_BASE_AC97C 0xfffd8000 +#define AT91_BASE_SYS 0xffffc000 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) + + +/* + * Internal Memory. + */ +#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ + +#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h new file mode 100644 index 00000000000..b15f11b7c08 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h @@ -0,0 +1,96 @@ +/* + * include/asm-arm/arch-at91/at91sam9rl_matrix.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_MATRIX_H +#define AT91SAM9RL_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + + +#endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index 7ef4eebe9f8..ef93c30a9c5 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -26,6 +26,8 @@ #define ARCH_ID_AT91SAM9XE256 0x329a93a0 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); @@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void) #define cpu_is_at91sam9263() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154d..0e51ad224ea 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -24,6 +24,8 @@ #include #elif defined(CONFIG_ARCH_AT91SAM9263) #include +#elif defined(CONFIG_ARCH_AT91SAM9RL) +#include #else #error "Unsupported AT91 processor" #endif diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f41636d607a..2df1ee12dfb 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -37,6 +37,11 @@ #define AT91SAM9_MASTER_CLOCK 99959500 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91SAM9RL) + +#define AT91SAM9_MASTER_CLOCK 100000000 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + #endif #endif -- cgit v1.2.3 From 54cb128037de499ea81626b0f37f9bb90e8db3d3 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 20:09:41 +0100 Subject: [ARM] 4372/1: Define byte sizes in asm-arm/sizes.h Define SZ_512, SZ_256 and SZ_16 in asm-arm/sizes.h. Remove the definitions from the at91*_devices.c files. (Dependent on ARM patch #4370/2) Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/sizes.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/asm-arm') diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h index 7f50ae0edf1..503843db156 100644 --- a/include/asm-arm/sizes.h +++ b/include/asm-arm/sizes.h @@ -24,6 +24,10 @@ #define __sizes_h 1 /* handy sizes */ +#define SZ_16 0x00000010 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + #define SZ_1K 0x00000400 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 -- cgit v1.2.3 From c53c9cf60e49119e97d38390849cac5b2f0a0981 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 21:01:28 +0100 Subject: [ARM] 4331/3: Support for Micrel/Kendin KS8695 processor Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-ks8695/debug-macro.S | 38 ++++++++++++ include/asm-arm/arch-ks8695/devices.h | 32 ++++++++++ include/asm-arm/arch-ks8695/dma.h | 17 ++++++ include/asm-arm/arch-ks8695/entry-macro.S | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/hardware.h | 49 ++++++++++++++++ include/asm-arm/arch-ks8695/io.h | 19 ++++++ include/asm-arm/arch-ks8695/irqs.h | 54 +++++++++++++++++ include/asm-arm/arch-ks8695/memory.h | 49 ++++++++++++++++ include/asm-arm/arch-ks8695/regs-gpio.h | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/regs-hpna.h | 25 ++++++++ include/asm-arm/arch-ks8695/regs-irq.h | 41 +++++++++++++ include/asm-arm/arch-ks8695/regs-lan.h | 65 +++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-mem.h | 89 ++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-misc.h | 97 +++++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-pci.h | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/regs-switch.h | 66 +++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-sys.h | 34 +++++++++++ include/asm-arm/arch-ks8695/regs-timer.h | 40 +++++++++++++ include/asm-arm/arch-ks8695/regs-uart.h | 92 +++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-wan.h | 65 +++++++++++++++++++++ include/asm-arm/arch-ks8695/system.h | 48 +++++++++++++++ include/asm-arm/arch-ks8695/timex.h | 20 +++++++ include/asm-arm/arch-ks8695/uncompress.h | 37 ++++++++++++ include/asm-arm/arch-ks8695/vmalloc.h | 19 ++++++ 24 files changed, 1155 insertions(+) create mode 100644 include/asm-arm/arch-ks8695/debug-macro.S create mode 100644 include/asm-arm/arch-ks8695/devices.h create mode 100644 include/asm-arm/arch-ks8695/dma.h create mode 100644 include/asm-arm/arch-ks8695/entry-macro.S create mode 100644 include/asm-arm/arch-ks8695/hardware.h create mode 100644 include/asm-arm/arch-ks8695/io.h create mode 100644 include/asm-arm/arch-ks8695/irqs.h create mode 100644 include/asm-arm/arch-ks8695/memory.h create mode 100644 include/asm-arm/arch-ks8695/regs-gpio.h create mode 100644 include/asm-arm/arch-ks8695/regs-hpna.h create mode 100644 include/asm-arm/arch-ks8695/regs-irq.h create mode 100644 include/asm-arm/arch-ks8695/regs-lan.h create mode 100644 include/asm-arm/arch-ks8695/regs-mem.h create mode 100644 include/asm-arm/arch-ks8695/regs-misc.h create mode 100644 include/asm-arm/arch-ks8695/regs-pci.h create mode 100644 include/asm-arm/arch-ks8695/regs-switch.h create mode 100644 include/asm-arm/arch-ks8695/regs-sys.h create mode 100644 include/asm-arm/arch-ks8695/regs-timer.h create mode 100644 include/asm-arm/arch-ks8695/regs-uart.h create mode 100644 include/asm-arm/arch-ks8695/regs-wan.h create mode 100644 include/asm-arm/arch-ks8695/system.h create mode 100644 include/asm-arm/arch-ks8695/timex.h create mode 100644 include/asm-arm/arch-ks8695/uncompress.h create mode 100644 include/asm-arm/arch-ks8695/vmalloc.h (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S new file mode 100644 index 00000000000..cd5f2fb1f06 --- /dev/null +++ b/include/asm-arm/arch-ks8695/debug-macro.S @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-ks8695/debug-macro.S + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Debug macros + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =KS8695_UART_PA @ physical base address + ldrne \rx, =KS8695_UART_VA @ virtual base address + .endm + + .macro senduart, rd, rx + str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register + .endm + + .macro busyuart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTE @ Holding & Shift registers empty? + beq 1001b + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTHRE @ Holding Register empty? + beq 1001b + .endm diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h new file mode 100644 index 00000000000..b0364dce463 --- /dev/null +++ b/include/asm-arm/arch-ks8695/devices.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-ks8695/devices.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DEVICES_H +#define __ASM_ARCH_DEVICES_H + +#include + + /* Ethernet */ +extern void __init ks8695_add_device_wan(void); +extern void __init ks8695_add_device_lan(void); +extern void __init ks8695_add_device_hpna(void); + + /* PCI */ +#define KS8695_MODE_PCI 0 +#define KS8695_MODE_MINIPCI 1 +#define KS8695_MODE_CARDBUS 2 + +struct ks8695_pci_cfg { + short mode; + int (*map_irq)(struct pci_dev *, u8, u8); +}; +extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); + +#endif diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h new file mode 100644 index 00000000000..e5159ed42a4 --- /dev/null +++ b/include/asm-arm/arch-ks8695/dma.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/arch-ks8695/dma.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S new file mode 100644 index 00000000000..e34bdf85920 --- /dev/null +++ b/include/asm-arm/arch-ks8695/entry-macro.S @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/entry-macro.S + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * Low-level IRQ helper macros for KS8695 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register + + teq \irqstat, #0 + beq 1001f + + mov \irqnr, #0 + + tst \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tst \irqstat, #0x0f + moveq \irqstat, \irqstat, lsr #4 + addeq \irqnr, \irqnr, #4 + tst \irqstat, #0x03 + moveq \irqstat, \irqstat, lsr #2 + addeq \irqnr, \irqnr, #2 + tst \irqstat, #0x01 + addeqs \irqnr, \irqnr, #1 +1001: + .endm diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h new file mode 100644 index 00000000000..cb732bff328 --- /dev/null +++ b/include/asm-arm/arch-ks8695/hardware.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-ks8695/hardware.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Memory Map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Physical RAM address. + */ +#define KS8695_SDRAM_PA 0x00000000 + + +/* + * We map an entire MiB with the System Configuration Registers in even + * though only 64KiB is needed. This makes it easier for use with the + * head debug code as the initial MMU setup only deals in L1 sections. + */ +#define KS8695_IO_PA 0x03F00000 +#define KS8695_IO_VA 0xF0000000 +#define KS8695_IO_SIZE SZ_1M + +#define KS8695_PCIMEM_PA 0x60000000 +#define KS8695_PCIMEM_SIZE SZ_512M + +#define KS8695_PCIIO_PA 0x80000000 +#define KS8695_PCIIO_SIZE SZ_64K + + +/* + * PCI support + */ +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 + +#endif diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h new file mode 100644 index 00000000000..8edc4bd6aad --- /dev/null +++ b/include/asm-arm/arch-ks8695/io.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-ks8695/io.h + * + * Copyright (C) 2006 Andrew Victor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h new file mode 100644 index 00000000000..8b1c4fe96a8 --- /dev/null +++ b/include/asm-arm/arch-ks8695/irqs.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-ks8695/irqs.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + + +#define NR_IRQS 32 + +/* + * IRQ definitions + */ +#define KS8695_IRQ_COMM_RX 0 +#define KS8695_IRQ_COMM_TX 1 +#define KS8695_IRQ_EXTERN0 2 +#define KS8695_IRQ_EXTERN1 3 +#define KS8695_IRQ_EXTERN2 4 +#define KS8695_IRQ_EXTERN3 5 +#define KS8695_IRQ_TIMER0 6 +#define KS8695_IRQ_TIMER1 7 +#define KS8695_IRQ_UART_TX 8 +#define KS8695_IRQ_UART_RX 9 +#define KS8695_IRQ_UART_LINE_STATUS 10 +#define KS8695_IRQ_UART_MODEM_STATUS 11 +#define KS8695_IRQ_LAN_RX_STOP 12 +#define KS8695_IRQ_LAN_TX_STOP 13 +#define KS8695_IRQ_LAN_RX_BUF 14 +#define KS8695_IRQ_LAN_TX_BUF 15 +#define KS8695_IRQ_LAN_RX_STATUS 16 +#define KS8695_IRQ_LAN_TX_STATUS 17 +#define KS8695_IRQ_HPNA_RX_STOP 18 +#define KS8695_IRQ_HPNA_TX_STOP 19 +#define KS8695_IRQ_HPNA_RX_BUF 20 +#define KS8695_IRQ_HPNA_TX_BUF 21 +#define KS8695_IRQ_HPNA_RX_STATUS 22 +#define KS8695_IRQ_HPNA_TX_STATUS 23 +#define KS8695_IRQ_BUS_ERROR 24 +#define KS8695_IRQ_WAN_RX_STOP 25 +#define KS8695_IRQ_WAN_TX_STOP 26 +#define KS8695_IRQ_WAN_RX_BUF 27 +#define KS8695_IRQ_WAN_TX_BUF 28 +#define KS8695_IRQ_WAN_RX_STATUS 29 +#define KS8695_IRQ_WAN_TX_STATUS 30 +#define KS8695_IRQ_WAN_LINK 31 + +#endif diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h new file mode 100644 index 00000000000..24f6a6e4a30 --- /dev/null +++ b/include/asm-arm/arch-ks8695/memory.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-ks8695/memory.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 Memory definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +/* + * Physical SRAM offset. + */ +#define PHYS_OFFSET KS8695_SDRAM_PA + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_PCI + +/* PCI mappings */ +#define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) +#define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) + +/* Platform-bus mapping */ +extern struct bus_type platform_bus_type; +#define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) +#define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ + __phys_to_virt(x) : __bus_to_virt(x); }) +#define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ + (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) +#define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) + +#else + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif + +#endif + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h new file mode 100644 index 00000000000..57fcf9fc82e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-gpio.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/regs-gpio.h + * + * Copyright (C) 2007 Andrew Victor + * + * KS8695 - GPIO control registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_GPIO_H +#define KS8695_GPIO_H + +#define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) +#define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) +#define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) + + +#define KS8695_IOPM (0x00) /* I/O Port Mode Register */ +#define KS8695_IOPC (0x04) /* I/O Port Control Register */ +#define KS8695_IOPD (0x08) /* I/O Port Data Register */ + + +/* Port Mode Register */ +#define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ + +/* Port Control Register */ +#define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ +#define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ +#define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ +#define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ +#define IOPC_IOEINT3_MODE(x) ((x) << 12) +#define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ +#define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ +#define IOPC_IOEINT2_MODE(x) ((x) << 8) +#define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ +#define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ +#define IOPC_IOEINT1_MODE(x) ((x) << 4) +#define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ +#define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ +#define IOPC_IOEINT0_MODE(x) ((x) << 0) + + /* Trigger Modes */ +#define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ +#define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ +#define IOPC_TM_RISING (2) /* Rising Edge Detection */ +#define IOPC_TM_FALLING (4) /* Falling Edge Detection */ +#define IOPC_TM_EDGE (6) /* Both Edge Detection */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h new file mode 100644 index 00000000000..14091cdec10 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-hpna.h @@ -0,0 +1,25 @@ +/* + * include/asm-arm/arch-ks8695/regs-wan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - HPNA Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_HPNA_H +#define KS8695_HPNA_H + +#define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) +#define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) +#define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) + + +/* + * HPNA registers + */ + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h new file mode 100644 index 00000000000..70b193f6b75 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-irq.h @@ -0,0 +1,41 @@ +/* + * include/asm-arm/arch-ks8695/regs-irq.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - IRQ registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_IRQ_H +#define KS8695_IRQ_H + +#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) +#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) +#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) + + +/* + * Interrupt Controller registers + */ +#define KS8695_INTMC (0x00) /* Mode Control Register */ +#define KS8695_INTEN (0x04) /* Interrupt Enable Register */ +#define KS8695_INTST (0x08) /* Interrupt Status Register */ +#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ +#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ +#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ +#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ +#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ +#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ +#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ +#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ +#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ +#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ +#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h new file mode 100644 index 00000000000..a63bd61c64e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-lan.h @@ -0,0 +1,65 @@ +/* + * include/asm-arm/arch-ks8695/regs-lan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - LAN Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_LAN_H +#define KS8695_LAN_H + +#define KS8695_LAN_OFFSET (0xF0000 + 0x8000) +#define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) +#define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) + + +/* + * LAN registers + */ +#define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ +#define KS8695_LMDRXC (0x04) /* DMA Receive Control */ +#define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ +#define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ +#define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ +#define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ +#define KS8695_LMAL (0x18) /* MAC Station Address Low */ +#define KS8695_LMAH (0x1c) /* MAC Station Address High */ +#define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ +#define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ + + +/* DMA Transmit Control Register */ +#define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ +#define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ +#define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ +#define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ +#define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ +#define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ +#define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ +#define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ +#define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ +#define LMDTXC_LMTE (1 << 0) /* TX Enable */ + +/* DMA Receive Control Register */ +#define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ +#define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ +#define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ +#define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ +#define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ +#define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ +#define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ +#define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ +#define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ +#define LMDRXC_LMRA (1 << 2) /* Receive All */ +#define LMDRXC_LMRE (1 << 1) /* RX Enable */ + +/* Additional Station Address High */ +#define LMAAH_E (1 << 31) /* Address Enabled */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h new file mode 100644 index 00000000000..76b38e0862e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-mem.h @@ -0,0 +1,89 @@ +/* + * include/asm-arm/arch-ks8695/regs-mem.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Memory Controller registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_MEM_H +#define KS8695_MEM_H + +#define KS8695_MEM_OFFSET (0xF0000 + 0x4000) +#define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) +#define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) + + +/* + * Memory Controller Registers + */ +#define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ +#define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ +#define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ +#define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ +#define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ +#define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ +#define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ +#define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ +#define KS8695_SDGCON (0x38) /* SDRAM General Control */ +#define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ +#define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ + + +/* External I/O Access Control Registers */ +#define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ +#define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ +#define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ +#define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ +#define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ + +/* ROM/SRAM/Flash Control Register */ +#define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ +#define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ +#define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ +#define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ +#define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ +#define PMC_NORMAL (0 << 0) +#define PMC_4WORD (1 << 0) +#define PMC_8WORD (2 << 0) +#define PMC_16WORD (3 << 0) + +/* External I/O and ROM/SRAM/Flash General Register */ +#define ERGCON_TMULT (3 << 28) /* Time Multiplier */ +#define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ +#define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ +#define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ +#define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ +#define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ + +/* SDRAM Control Register */ +#define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ +#define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ +#define SDCON_DBCAB (3 << 8) /* Column Address Bits */ +#define SDCON_DBBNUM (1 << 3) /* Number of Banks */ +#define SDCON_DBDBW (3 << 1) /* Data Bus Width */ + +/* SDRAM General Control Register */ +#define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ +#define SDGCON_SDCAS (3 << 0) /* CAS latency */ + +/* SDRAM Buffer Control Register */ +#define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ +#define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ +#define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ +#define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ +#define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ +#define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ +#define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ +#define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ + +/* SDRAM Refresh Timer Register */ +#define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h new file mode 100644 index 00000000000..632ca6601a9 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-misc.h @@ -0,0 +1,97 @@ +/* + * include/asm-arm/arch-ks8695/regs-misc.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Miscellaneous Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_MISC_H +#define KS8695_MISC_H + +#define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) +#define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) +#define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) + + +/* + * Miscellaneous registers + */ +#define KS8695_DID (0x00) /* Device ID */ +#define KS8695_RID (0x04) /* Revision ID */ +#define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ +#define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ +#define KS8695_WPPM (0x10) /* WAN PHY Power Management */ +#define KS8695_PPS (0x1c) /* PHY PowerSave */ + +/* Device ID Register */ +#define DID_ID (0xffff << 0) /* Device ID */ + +/* Revision ID Register */ +#define RID_SUBID (0xf << 4) /* Sub-Device ID */ +#define RID_REVISION (0xf << 0) /* Revision ID */ + +/* HPNA Miscellaneous Control Register */ +#define HMC_HSS (1 << 1) /* Speed */ +#define HMC_HDS (1 << 0) /* Duplex */ + +/* WAN Miscellaneous Control Register */ +#define WMC_WANC (1 << 30) /* Auto-negotiation complete */ +#define WMC_WANR (1 << 29) /* Auto-negotiation restart */ +#define WMC_WANAP (1 << 28) /* Advertise Pause */ +#define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ +#define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ +#define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ +#define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ +#define WMC_WLS (1 << 23) /* Link status */ +#define WMC_WDS (1 << 22) /* Duplex status */ +#define WMC_WSS (1 << 21) /* Speed status */ +#define WMC_WLPP (1 << 20) /* Link Partner Pause */ +#define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ +#define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ +#define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ +#define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ +#define WMC_WAND (1 << 15) /* Auto-negotiation disable */ +#define WMC_WANF100 (1 << 14) /* Force 100 */ +#define WMC_WANFF (1 << 13) /* Force FDX */ +#define WMC_WLED1S (7 << 4) /* LED1 Select */ +#define WLED1S_SPEED (0 << 4) +#define WLED1S_LINK (1 << 4) +#define WLED1S_DUPLEX (2 << 4) +#define WLED1S_COLLISION (3 << 4) +#define WLED1S_ACTIVITY (4 << 4) +#define WLED1S_FDX_COLLISION (5 << 4) +#define WLED1S_LINK_ACTIVITY (6 << 4) +#define WMC_WLED0S (7 << 0) /* LED0 Select */ +#define WLED0S_SPEED (0 << 0) +#define WLED0S_LINK (1 << 0) +#define WLED0S_DUPLEX (2 << 0) +#define WLED0S_COLLISION (3 << 0) +#define WLED0S_ACTIVITY (4 << 0) +#define WLED0S_FDX_COLLISION (5 << 0) +#define WLED0S_LINK_ACTIVITY (6 << 0) + +/* WAN PHY Power Management Register */ +#define WPPM_WLPBK (1 << 14) /* Local Loopback */ +#define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ +#define WPPM_WPI (1 << 12) /* PHY isolate */ +#define WPPM_WFL (1 << 10) /* Force link */ +#define WPPM_MDIXS (1 << 9) /* MDIX Status */ +#define WPPM_FEF (1 << 8) /* Far End Fault */ +#define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ +#define WPPM_TXDIS (1 << 6) /* Disable transmitter */ +#define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ +#define WPPM_PD (1 << 4) /* Power Down */ +#define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ +#define WPPM_FMDX (1 << 2) /* Force MDIX */ +#define WPPM_LPBK (1 << 1) /* MAX Loopback */ + +/* PHY Power Save Register */ +#define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h new file mode 100644 index 00000000000..286d6d488df --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-pci.h @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/regs-pci.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - PCI bridge registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define KS8695_PCI_OFFSET (0xF0000 + 0x2000) +#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) +#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) + + +#define KS8695_CRCFID (0x000) /* Configuration: Identification */ +#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ +#define KS8695_CRCFRV (0x008) /* Configuration: Revision */ +#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ +#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ +#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ +#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ +#define KS8695_PBCA (0x100) /* Bridge Configuration Address */ +#define KS8695_PBCD (0x104) /* Bridge Configuration Data */ +#define KS8695_PBM (0x200) /* Bridge Mode */ +#define KS8695_PBCS (0x204) /* Bridge Control and Status */ +#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ +#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ +#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ +#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ +#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ +#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ +#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ +#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ + + +/* Configuration: Identification */ + +/* Configuration: Command and Status */ + +/* Configuration: Revision */ + + + +#define CFRV_GUEST (1 << 23) + +#define PBCA_TYPE1 (1) +#define PBCA_ENABLE (1 << 31) + + diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h new file mode 100644 index 00000000000..5f37be3f2f6 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-switch.h @@ -0,0 +1,66 @@ +/* + * include/asm-arm/arch-ks8695/regs-switch.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - Switch Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_SWITCH_H +#define KS8695_SWITCH_H + +#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) +#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) +#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) + + +/* + * Switch registers + */ +#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ +#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ +#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ + +#define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ + +#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ +#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ +#define KS8695_SEIAC (0x50) /* Indirect Access Control */ +#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ +#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ +#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ +#define KS8695_SEAFC (0x60) /* Advance Feature Control */ +#define KS8695_SEDSCPH (0x64) /* TOS Priority High */ +#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ +#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ +#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ +#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ +#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ + + +/* Switch Engine Control 0 */ +#define SEC0_LLED1S (7 << 25) /* LED1 Select */ +#define LLED1S_SPEED (0 << 25) +#define LLED1S_LINK (1 << 25) +#define LLED1S_DUPLEX (2 << 25) +#define LLED1S_COLLISION (3 << 25) +#define LLED1S_ACTIVITY (4 << 25) +#define LLED1S_FDX_COLLISION (5 << 25) +#define LLED1S_LINK_ACTIVITY (6 << 25) +#define SEC0_LLED0S (7 << 22) /* LED0 Select */ +#define LLED0S_SPEED (0 << 22) +#define LLED0S_LINK (1 << 22) +#define LLED0S_DUPLEX (2 << 22) +#define LLED0S_COLLISION (3 << 22) +#define LLED0S_ACTIVITY (4 << 22) +#define LLED0S_FDX_COLLISION (5 << 22) +#define LLED0S_LINK_ACTIVITY (6 << 22) +#define SEC0_ENABLE (1 << 0) /* Enable Switch */ + + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h new file mode 100644 index 00000000000..f3179815b8e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-sys.h @@ -0,0 +1,34 @@ +/* + * include/asm-arm/arch-ks8695/regs-sys.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - System control registers and bit definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_SYS_H +#define KS8695_SYS_H + +#define KS8695_SYS_OFFSET (0xF0000 + 0x0000) +#define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) +#define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) + + +#define KS8695_SYSCFG (0x00) /* System Configuration Register */ +#define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ + + +/* System Configuration Register */ +#define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ + +/* System Clock and Bus Control Register */ +#define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ +#define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h new file mode 100644 index 00000000000..0a9f7f99ec5 --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-timer.h @@ -0,0 +1,40 @@ +/* + * include/asm-arm/arch-ks8695/regs-timer.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Timer registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_TIMER_H +#define KS8695_TIMER_H + +#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) +#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) +#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) + + +/* + * Timer registers + */ +#define KS8695_TMCON (0x00) /* Timer Control Register */ +#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ +#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ +#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ +#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ + + +/* Timer Control Register */ +#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ +#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ + +/* Timer0 Timeout Counter Register */ +#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h new file mode 100644 index 00000000000..a27cb20502a --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-uart.h @@ -0,0 +1,92 @@ +/* + * linux/include/asm-arm/arch-ks8695/regs-uart.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - UART register and bit definitions. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef KS8695_UART_H +#define KS8695_UART_H + +#define KS8695_UART_OFFSET (0xF0000 + 0xE000) +#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) +#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) + + +/* + * UART registers + */ +#define KS8695_URRB (0x00) /* Receive Buffer Register */ +#define KS8695_URTH (0x04) /* Transmit Holding Register */ +#define KS8695_URFC (0x08) /* FIFO Control Register */ +#define KS8695_URLC (0x0C) /* Line Control Register */ +#define KS8695_URMC (0x10) /* Modem Control Register */ +#define KS8695_URLS (0x14) /* Line Status Register */ +#define KS8695_URMS (0x18) /* Modem Status Register */ +#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ +#define KS8695_USR (0x20) /* Status Register */ + + +/* FIFO Control Register */ +#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ +#define URFC_URFRT_1 (0 << 6) +#define URFC_URFRT_4 (1 << 6) +#define URFC_URFRT_8 (2 << 6) +#define URFC_URFRT_14 (3 << 6) +#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ +#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ +#define URFC_URFE (1 << 0) /* FIFO Enable */ + +/* Line Control Register */ +#define URLC_URSBC (1 << 6) /* Set Break Condition */ +#define URLC_PARITY (7 << 3) /* Parity */ +#define URPE_NONE (0 << 3) +#define URPE_ODD (1 << 3) +#define URPE_EVEN (3 << 3) +#define URPE_MARK (5 << 3) +#define URPE_SPACE (7 << 3) +#define URLC_URSB (1 << 2) /* Stop Bits */ +#define URLC_URCL (3 << 0) /* Character Length */ +#define URCL_5 (0 << 0) +#define URCL_6 (1 << 0) +#define URCL_7 (2 << 0) +#define URCL_8 (3 << 0) + +/* Modem Control Register */ +#define URMC_URLB (1 << 4) /* Loop-back mode */ +#define URMC_UROUT2 (1 << 3) /* OUT2 signal */ +#define URMC_UROUT1 (1 << 2) /* OUT1 signal */ +#define URMC_URRTS (1 << 1) /* Request to Send */ +#define URMC_URDTR (1 << 0) /* Data Terminal Ready */ + +/* Line Status Register */ +#define URLS_URRFE (1 << 7) /* Receive FIFO Error */ +#define URLS_URTE (1 << 6) /* Transmit Empty */ +#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ +#define URLS_URBI (1 << 4) /* Break Interrupt */ +#define URLS_URFE (1 << 3) /* Framing Error */ +#define URLS_URPE (1 << 2) /* Parity Error */ +#define URLS_URROE (1 << 1) /* Receive Overrun Error */ +#define URLS_URDR (1 << 0) /* Receive Data Ready */ + +/* Modem Status Register */ +#define URMS_URDCD (1 << 7) /* Data Carrier Detect */ +#define URMS_URRI (1 << 6) /* Ring Indicator */ +#define URMS_URDSR (1 << 5) /* Data Set Ready */ +#define URMS_URCTS (1 << 4) /* Clear to Send */ +#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ +#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ +#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ + +/* Status Register */ +#define USR_UTI (1 << 0) /* Timeout Indication */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h new file mode 100644 index 00000000000..52e35b0d65e --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-wan.h @@ -0,0 +1,65 @@ +/* + * include/asm-arm/arch-ks8695/regs-wan.h + * + * Copyright (C) 2006 Andrew Victor + * + * KS8695 - WAN Registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_WAN_H +#define KS8695_WAN_H + +#define KS8695_WAN_OFFSET (0xF0000 + 0x6000) +#define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) +#define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) + + +/* + * WAN registers + */ +#define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ +#define KS8695_WMDRXC (0x04) /* DMA Receive Control */ +#define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ +#define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ +#define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ +#define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ +#define KS8695_WMAL (0x18) /* MAC Station Address Low */ +#define KS8695_WMAH (0x1c) /* MAC Station Address High */ +#define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ +#define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ + + +/* DMA Transmit Control Register */ +#define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ +#define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ +#define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ +#define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ +#define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ +#define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ +#define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ +#define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ +#define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ +#define WMDTXC_WMTE (1 << 0) /* TX Enable */ + +/* DMA Receive Control Register */ +#define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ +#define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ +#define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ +#define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ +#define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ +#define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ +#define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ +#define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ +#define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ +#define WMDRXC_WMRA (1 << 2) /* Receive All */ +#define WMDRXC_WMRE (1 << 0) /* RX Enable */ + +/* Additional Station Address High */ +#define WMAAH_E (1 << 31) /* Address Enabled */ + + +#endif diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h new file mode 100644 index 00000000000..3bc28106d93 --- /dev/null +++ b/include/asm-arm/arch-ks8695/system.h @@ -0,0 +1,48 @@ +/* + * include/asm-arm/arch-s3c2410/system.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * KS8695 - System function defines and includes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +static void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks, + */ + cpu_do_idle(); + +} + +static void arch_reset(char mode) +{ + unsigned int reg; + + if (mode == 's') + cpu_reset(0); + + /* disable timer0 */ + reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + + /* enable watchdog mode */ + __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); + + /* re-enable timer0 */ + __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); +} + +#endif diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h new file mode 100644 index 00000000000..8320d528b90 --- /dev/null +++ b/include/asm-arm/arch-ks8695/timex.h @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-ks8695/timex.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * KS8695 - Time Parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* timers are derived from MCLK, which is 25MHz */ +#define CLOCK_TICK_RATE 25000000 + +#endif diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h new file mode 100644 index 00000000000..733a50855b5 --- /dev/null +++ b/include/asm-arm/arch-ks8695/uncompress.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-ks8695/uncompress.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Kernel uncompressor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include + +static void putc(char c) +{ + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) + barrier(); + + __raw_writel(c, KS8695_UART_PA + KS8695_URTH); +} + +static inline void flush(void) +{ + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h new file mode 100644 index 00000000000..d1d88e58117 --- /dev/null +++ b/include/asm-arm/arch-ks8695/vmalloc.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-ks8695/vmalloc.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 vmalloc definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) + +#endif -- cgit v1.2.3 From 641e79129a56a4c50be1aed0fa713f440b46a440 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 12 May 2007 15:25:50 +0100 Subject: [ARM] Use new get_irqnr_preamble Use the new get_irqnr_preamble macro to move the address of the IRQ controller outside the IRQ handling loop. Signed-off-by: Russell King --- include/asm-arm/arch-cl7500/entry-macro.S | 8 ++++++++ include/asm-arm/arch-ebsa110/entry-macro.S | 2 +- include/asm-arm/arch-ebsa285/entry-macro.S | 16 ++++++++-------- include/asm-arm/arch-realview/entry-macro.S | 2 +- include/asm-arm/arch-rpc/entry-macro.S | 8 ++++++++ include/asm-arm/arch-sa1100/entry-macro.S | 8 ++++---- include/asm-arm/arch-versatile/entry-macro.S | 2 +- include/asm-arm/hardware/entry-macro-iomd.S | 28 +++++++++++----------------- 8 files changed, 42 insertions(+), 32 deletions(-) (limited to 'include/asm-arm') diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S index 0cfb89b229d..038b761fdad 100644 --- a/include/asm-arm/arch-cl7500/entry-macro.S +++ b/include/asm-arm/arch-cl7500/entry-macro.S @@ -1,6 +1,14 @@ #include #include + + .equ ioc_base_high, IOC_BASE & 0xff000000 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 + .macro get_irqnr_preamble, base, tmp + mov \base, #ioc_base_high @ point at IOC + .if ioc_base_low + orr \base, \base, #ioc_base_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S index aa23c5d6c69..f242be5c49b 100644 --- a/include/asm-arm/arch-ebsa110/entry-macro.S +++ b/include/asm-arm/arch-ebsa110/entry-macro.S @@ -16,13 +16,13 @@ .endm .macro get_irqnr_preamble, base, tmp + mov \base, #IRQ_STAT .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, stat, base, tmp - mov \base, #IRQ_STAT ldrb \stat, [\base] @ get interrupts mov \irqnr, #0 tst \stat, #15 diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S index 4203dbf1066..e63064edb73 100644 --- a/include/asm-arm/arch-ebsa285/entry-macro.S +++ b/include/asm-arm/arch-ebsa285/entry-macro.S @@ -11,24 +11,24 @@ #include #include + .equ dc21285_high, ARMCSR_BASE & 0xff000000 + .equ dc21285_low, ARMCSR_BASE & 0x00ffffff + .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp + mov \base, #dc21285_high + .if dc21285_low + orr \base, \base, #dc21285_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 .endm - .equ dc21285_high, ARMCSR_BASE & 0xff000000 - .equ dc21285_low, ARMCSR_BASE & 0x00ffffff - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #dc21285_high - .if dc21285_low - orr r4, r4, #dc21285_low - .endif - ldr \irqstat, [r4, #0x180] @ get interrupts + ldr \irqstat, [\base, #0x180] @ get interrupts mov \irqnr, #IRQ_SDRAMPARITY tst \irqstat, #IRQ_MASK_SDRAMPARITY diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 138838d4ad7..3b4e2076603 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -14,6 +14,7 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 @@ -40,7 +41,6 @@ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ ldr \tmp, =1021 diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S index 0cfb89b229d..038b761fdad 100644 --- a/include/asm-arm/arch-rpc/entry-macro.S +++ b/include/asm-arm/arch-rpc/entry-macro.S @@ -1,6 +1,14 @@ #include #include + + .equ ioc_base_high, IOC_BASE & 0xff000000 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 + .macro get_irqnr_preamble, base, tmp + mov \base, #ioc_base_high @ point at IOC + .if ioc_base_low + orr \base, \base, #ioc_base_low + .endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S index 02896762934..127db4aaf4f 100644 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ b/include/asm-arm/arch-sa1100/entry-macro.S @@ -12,16 +12,16 @@ .endm .macro get_irqnr_preamble, base, tmp + mov \base, #0xfa000000 @ ICIP = 0xfa050000 + add \base, \base, #0x00050000 .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #0xfa000000 @ ICIP = 0xfa050000 - add r4, r4, #0x00050000 - ldr \irqstat, [r4] @ get irqs - ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004 + ldr \irqstat, [\base] @ get irqs + ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 ands \irqstat, \irqstat, \irqnr mov \irqnr, #0 beq 1001f diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index 0fae002637a..924d1a8fe36 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S @@ -14,13 +14,13 @@ .endm .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status mov \irqnr, #0 teq \irqstat, #0 diff --git a/include/asm-arm/hardware/entry-macro-iomd.S b/include/asm-arm/hardware/entry-macro-iomd.S index fbed08f298d..9bb580a5b15 100644 --- a/include/asm-arm/hardware/entry-macro-iomd.S +++ b/include/asm-arm/hardware/entry-macro-iomd.S @@ -11,8 +11,6 @@ /* IOC / IOMD based hardware */ #include - .equ ioc_base_high, IOC_BASE & 0xff000000 - .equ ioc_base_low, IOC_BASE & 0x00ff0000 .macro disable_fiq mov r12, #ioc_base_high .if ioc_base_low @@ -22,33 +20,29 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov r4, #ioc_base_high @ point at IOC - .if ioc_base_low - orr r4, r4, #ioc_base_low - .endif - ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first - ldr \base, =irq_prio_h + ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first + ldr \tmp, =irq_prio_h teq \irqstat, #0 #ifdef IOMD_BASE - ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma - addeq \base, \base, #256 @ irq_prio_h table size + ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma + addeq \tmp, \tmp, #256 @ irq_prio_h table size teqeq \irqstat, #0 bne 2406f #endif - ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority - addeq \base, \base, #256 @ irq_prio_d table size + ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority + addeq \tmp, \tmp, #256 @ irq_prio_d table size teqeq \irqstat, #0 #ifdef IOMD_IRQREQC - ldreqb \irqstat, [r4, #IOMD_IRQREQC] - addeq \base, \base, #256 @ irq_prio_l table size + ldreqb \irqstat, [\base, #IOMD_IRQREQC] + addeq \tmp, \tmp, #256 @ irq_prio_l table size teqeq \irqstat, #0 #endif #ifdef IOMD_IRQREQD - ldreqb \irqstat, [r4, #IOMD_IRQREQD] - addeq \base, \base, #256 @ irq_prio_lc table size + ldreqb \irqstat, [\base, #IOMD_IRQREQD] + addeq \tmp, \tmp, #256 @ irq_prio_lc table size teqeq \irqstat, #0 #endif -2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number +2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number .endm /* -- cgit v1.2.3