From 287050fe13bf34824f03b4351002b0e2db4ee5cb Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 24 Jul 2007 15:23:20 +0800 Subject: Blackfin arch: cleanup and standardize anomaly.h file format -- no functional changes Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 67 ++++++++++--------------------- 1 file changed, 22 insertions(+), 45 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index aca1d4ba145..964a1c0ea63 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -1,74 +1,51 @@ - /* - * File: include/asm-blackfin/mach-bf548/anomaly.h - * Based on: - * Author: - * - * Created: - * Description: - * - * Rev: - * - * Modified: - * + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. - * If not, write to the Free Software Foundation, - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Copyright (C) 2004-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ + #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - slot1 and store of a P register in slot 2 is not - supported */ + * slot1 and store of a P register in slot 2 is not + * supported */ #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - Channel DMA stops */ + * Channel DMA stops */ #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - registers. */ + * registers. */ #define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the - Shadow of a Conditional Branch */ + * Shadow of a Conditional Branch */ #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - interrupt not functional */ + * interrupt not functional */ #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - SPORT external receive and transmit clocks. */ + * SPORT external receive and transmit clocks. */ #define ANOMALY_05000272 /* Certain data cache write through modes fail for - VDDint <=0.9V */ + * VDDint <=0.9V */ #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - not restored */ + * not restored */ #define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the - Boundary of Reserved Memory */ + * Boundary of Reserved Memory */ #define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and - LC Registers Are Interrupted */ + * LC Registers Are Interrupted */ #define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ #define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to - the USB FIFO Simultaneously */ + * the USB FIFO Simultaneously */ #define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() - function */ + * function */ #define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional - */ + * */ #define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ #define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM - Skew */ + * Skew */ #define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ #define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration - of Host DMA Port */ + * of Host DMA Port */ #define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent - Allowed Configuration on Host DMA Port */ + * Allowed Configuration on Host DMA Port */ #define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ #endif /* _MACH_ANOMALY_H_ */ -- cgit v1.2.3 From 1aafd9091226a02b481298315f959f777294684e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 11:19:14 +0800 Subject: Blackfin arch: revise anomaly handling by basing things on the compiler not the kconfig defines revise anomaly handling by basing things on the compiler not the kconfig defines, so the header is stable and usable outside of the kernel. This also allows us to move some code from preprocessing to compiling (gcc culls dead code) which should help with code quality (readability, catch minor bugs, etc...). Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 94 ++++++++++++++++++------------- 1 file changed, 55 insertions(+), 39 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 964a1c0ea63..952f03e140f 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -6,46 +6,62 @@ * Licensed under the GPL-2 or later. */ +/* This file shoule be up to date with: + * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List + */ + #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ -#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in - * slot1 and store of a P register in slot 2 is not - * supported */ -#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive - * Channel DMA stops */ -#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR - * registers. */ -#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the - * Shadow of a Conditional Branch */ -#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event - * interrupt not functional */ -#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on - * SPORT external receive and transmit clocks. */ -#define ANOMALY_05000272 /* Certain data cache write through modes fail for - * VDDint <=0.9V */ -#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is - * not restored */ -#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the - * Boundary of Reserved Memory */ -#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and - * LC Registers Are Interrupted */ -#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to - * the USB FIFO Simultaneously */ -#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() - * function */ -#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional - * */ -#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ -#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM - * Skew */ -#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration - * of Host DMA Port */ -#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent - * Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ +#define ANOMALY_05000255 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (1) +/* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000325 (1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (1) +/* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000330 (1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000125 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000311 (0) -#endif /* _MACH_ANOMALY_H_ */ +#endif -- cgit v1.2.3 From 60e9356d770ca3622fe5e84680b78fc376e53fbf Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 11:56:01 +0800 Subject: Blackfin arch: update BF54x anomaly list Signed-off-by: Mike Frysinger Signed-off-by: Roy Huang Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 952f03e140f..37e0bd22b64 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -27,6 +27,8 @@ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) +/* False Hardware Error Exception when ISR context is not restored */ +#define ANOMALY_05000281 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ @@ -59,6 +61,7 @@ #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) #define ANOMALY_05000244 (0) +#define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) -- cgit v1.2.3 From d5148ffa600e6a655b458bedc593020e0574f967 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 11:57:42 +0800 Subject: Blackfin arch: use the [CS]SYNC() macros which include anomaly workarounds rather than __builtin_bfin_[cs]sync() Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index cdf29e75ea5..10475bbfc7d 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -60,7 +60,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write32(SIC_IWR2, 0); bfin_write16(VR_CTL, val); - __builtin_bfin_ssync(); + SSYNC(); local_irq_save(flags); asm("IDLE;"); -- cgit v1.2.3 From 36a1548f99e54520f049a703e1b91bae95e72481 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 12:01:19 +0800 Subject: Blackfin arch: reorganize headers slightly so we can be sure things are defined early enough Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/cdefBF54x_base.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 10475bbfc7d..aefab3f618c 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -31,6 +31,8 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H +#include + #include "defBF54x_base.h" #include -- cgit v1.2.3 From bc8c84c947ad65cd2850c43f96bea825e426f9eb Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 5 Aug 2007 17:32:25 +0800 Subject: Blackfin arch: update to latest anomaly sheets Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 37e0bd22b64..224837845c7 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision B, April 6, 2007; ADSP-BF549 Silicon Anomaly List + * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -21,14 +21,14 @@ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* False Hardware Error Exception when ISR context is not restored */ #define ANOMALY_05000281 (1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ @@ -55,6 +55,18 @@ #define ANOMALY_05000337 (1) /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ #define ANOMALY_05000338 (1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (1) +/* USB Calibration Value Is Not Intialized */ +#define ANOMALY_05000346 (1) +/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) -- cgit v1.2.3 From 301af2952b35fa527c89b4c0c0c1003d50afc378 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 24 Jul 2007 15:35:53 +0800 Subject: Blackfin arch: Finalize the generic gpio support - add gpio_to_irq and irq_to_gpio Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/irq.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index e548d3cd81e..21f06f710be 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -337,6 +337,8 @@ Events (highest priority) EMU 0 #define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ #define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ +#define GPIO_IRQ_BASE IRQ_PA0 + #ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PJ15+1) #else -- cgit v1.2.3 From 40d63406a0dfc070fff9336c182619a0b167f165 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 10 Oct 2007 22:55:30 +0800 Subject: Blackfin arch: store labels so we later know who allocated GPIO/Peripheral resources Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/gpio.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h index dbf66bcabe3..cb8b0f15c9a 100644 --- a/include/asm-blackfin/mach-bf548/gpio.h +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -209,8 +209,3 @@ struct gpio_port_t { unsigned short dummy7; unsigned int port_mux; }; - -int gpio_request(unsigned short gpio, const char *label); -void peripheral_free(unsigned short per); -int peripheral_request_list(unsigned short per[], const char *label); -void peripheral_free_list(unsigned short per[]); -- cgit v1.2.3 From 1708268f7ee5177c35826f047b91d7324f099ab0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 11:50:42 +0800 Subject: Blackfin arch: scrub remaining ASSEMBLY usage since the switch to __ASSEMBLY__ Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/blackfin.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 791218fe7d9..19e84dd4c99 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -54,7 +54,7 @@ #include "defBF549.h" #endif -#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#if !defined(__ASSEMBLY__) #ifdef CONFIG_BF542 #include "cdefBF542.h" #endif -- cgit v1.2.3 From b99ab54d4f11141b2ef3e50c3543b7243d3f49fb Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 11 Oct 2007 10:57:54 +0800 Subject: Blackfin serial driver: use new GPIO API Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 39 +++++++++++------------ 1 file changed, 19 insertions(+), 20 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 2f4afc90db1..f21a1620e6b 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -1,5 +1,6 @@ #include #include +#include #define NR_PORTS 4 @@ -143,50 +144,48 @@ struct bfin_serial_res bfin_serial_resource[] = { int nr_ports = ARRAY_SIZE(bfin_serial_resource); +#define DRIVER_NAME "bfin-uart" + static void bfin_serial_hw_init(struct bfin_serial_port *uart) { #ifdef CONFIG_SERIAL_BFIN_UART0 - /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ - bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); - bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); + peripheral_request(P_UART0_TX, DRIVER_NAME); + peripheral_request(P_UART0_RX, DRIVER_NAME); #endif #ifdef CONFIG_SERIAL_BFIN_UART1 - /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ - bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); - bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); + peripheral_request(P_UART1_TX, DRIVER_NAME); + peripheral_request(P_UART1_RX, DRIVER_NAME); + #ifdef CONFIG_BFIN_UART1_CTSRTS - /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ - bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); - bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); + peripheral_request(P_UART1_RTS, DRIVER_NAME); + peripheral_request(P_UART1_CTS DRIVER_NAME); #endif #endif #ifdef CONFIG_SERIAL_BFIN_UART2 - /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ - bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); + peripheral_request(P_UART2_TX, DRIVER_NAME); + peripheral_request(P_UART2_RX, DRIVER_NAME); #endif #ifdef CONFIG_SERIAL_BFIN_UART3 - /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ - bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); + peripheral_request(P_UART3_TX, DRIVER_NAME); + peripheral_request(P_UART3_RX, DRIVER_NAME); + #ifdef CONFIG_BFIN_UART3_CTSRTS - /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ - bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); - bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); + peripheral_request(P_UART3_RTS, DRIVER_NAME); + peripheral_request(P_UART3_CTS DRIVER_NAME); #endif #endif SSYNC(); #ifdef CONFIG_SERIAL_BFIN_CTSRTS if (uart->cts_pin >= 0) { - gpio_request(uart->cts_pin, NULL); + gpio_request(uart->cts_pin, DRIVER_NAME); gpio_direction_input(uart->cts_pin); } if (uart->rts_pin >= 0) { - gpio_request(uart->rts_pin, NULL); + gpio_request(uart->rts_pin, DRIVER_NAME); gpio_direction_output(uart->rts_pin); } #endif -- cgit v1.2.3 From f16295e7e7f2a2a15876f570f10d6dc8f1f36ab8 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 3 Aug 2007 18:07:17 +0800 Subject: Blackfin arch: Fix CCLK and SCLK checks Fix CCLK and SCLK checks, combine all arch checks into one file for maintance. Checkins that remove more lines than they add are always good. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/bf548.h | 87 --------------------------------- 1 file changed, 87 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 9498313a2cb..50306a84662 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -106,93 +106,6 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) -#define MAX_VC 650000000 -#define MIN_VC 50000000 - -/********************************PLL Settings **************************************/ -#ifdef CONFIG_BFIN_KERNEL_CLOCK -#if (CONFIG_VCO_MULT < 0) -#error "VCO Multiplier is less than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT == 0) -#error "VCO Multiplier should be greater than 0. Please select a different value" -#endif - -#if (CONFIG_VCO_MULT > 64) -#error "VCO Multiplier is more than 64. Please select a different value" -#endif - -#ifndef CONFIG_CLKIN_HALF -#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) -#else -#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) -#endif - -#ifndef CONFIG_PLL_BYPASS -#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) -#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#if (CONFIG_SCLK_DIV < 1) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_SCLK_DIV > 15) -#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" -#endif - -#if (CONFIG_CCLK_DIV != 1) -#if (CONFIG_CCLK_DIV != 2) -#if (CONFIG_CCLK_DIV != 4) -#if (CONFIG_CCLK_DIV != 8) -#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" -#endif -#endif -#endif -#endif - -#if (CONFIG_VCO_HZ > MAX_VC) -#error "VCO selected is more than maximum value. Please change the VCO multipler" -#endif - -#if (CONFIG_SCLK_HZ > 133000000) -#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ < 27000000) -#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" -#endif - -#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) -#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) -#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) -#error "Please select sclk less than cclk" -#endif -#endif -#endif - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -#endif /* CONFIG_BFIN_KERNEL_CLOCK */ - #ifdef CONFIG_BF542 #define CPU "BF542" #define CPUID 0x027c8000 -- cgit v1.2.3 From 3bebca2d20796dd3dc62c5d3e74148087c7ce5bd Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Wed, 10 Oct 2007 23:55:26 +0800 Subject: Blackfin arch: to do some consolidation of common code and common name spaces now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/bf548.h | 67 +++---------------------------- include/asm-blackfin/mach-bf548/mem_map.h | 24 +++++------ 2 files changed, 18 insertions(+), 73 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 50306a84662..7e6d349beb0 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -52,12 +52,12 @@ /***************************/ -#define BLKFIN_DSUBBANKS 4 -#define BLKFIN_DWAYS 2 -#define BLKFIN_DLINES 64 -#define BLKFIN_ISUBBANKS 4 -#define BLKFIN_IWAYS 4 -#define BLKFIN_ILINES 32 +#define BFIN_DSUBBANKS 4 +#define BFIN_DWAYS 2 +#define BFIN_DLINES 64 +#define BFIN_ISUBBANKS 4 +#define BFIN_IWAYS 4 +#define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 @@ -126,59 +126,4 @@ #define CPUID 0x0 #endif -#if (CONFIG_MEM_SIZE % 4) -#error "SDRAM mem size must be multible of 4MB" -#endif - -#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) -#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) -#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158_WORKAROUND 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#else /*Write Through */ -#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ - | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#endif - - -#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) -#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) - -#define SIZE_1K 0x00000400 /* 1K */ -#define SIZE_4K 0x00001000 /* 4K */ -#define SIZE_1M 0x00100000 /* 1M */ -#define SIZE_4M 0x00400000 /* 4M */ - -#define MAX_CPLBS (16 * 2) - -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - #endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index 72d80e8a6e8..ec1597e3183 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -51,10 +51,10 @@ /* Level 1 Memory */ /* Memory Map for ADSP-BF548 processors */ -#ifdef CONFIG_BLKFIN_ICACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif #define L1_CODE_START 0xFFA00000 @@ -63,29 +63,29 @@ #define L1_CODE_LENGTH 0xC000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ /* Scratch Pad Memory */ -- cgit v1.2.3 From 2cbfe107434b9651168afb21015f3285e02beed3 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Sun, 5 Aug 2007 15:31:16 +0800 Subject: Blackfin arch: kill ezkit548 compiling warning kill ezkit548 compiling warning: - include/asm/cplb.h:42:5: warning: "ANOMALY_05000158" is not defined Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 224837845c7..d3638e3dfa9 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -70,6 +70,7 @@ /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) +#define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) #define ANOMALY_05000244 (0) -- cgit v1.2.3 From 0174dd59bb5f343e8981b5ea7a3dc782fad5b644 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 5 Aug 2007 16:53:10 +0800 Subject: Blackfin arch: make sure to stub out ANOMALY_05000230 were appropriate Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index d3638e3dfa9..0d12dbe5232 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -73,6 +73,7 @@ #define ANOMALY_05000158 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000230 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) -- cgit v1.2.3 From 55249e9e3d07617e00cc6c52b83f7d1a7eb7e64d Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 11 Oct 2007 00:06:31 +0800 Subject: Blackfin arch: For compatibility reasons change IRQ_XXX_ERR into IRQ_XXX_ERROR like on any other supported Blackfin derivative Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/irq.h | 589 ++++++++++++++++++---------------- 1 file changed, 308 insertions(+), 281 deletions(-) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 21f06f710be..3b08cf9bd6f 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -55,287 +55,286 @@ Events (highest priority) EMU 0 /* The ABSTRACT IRQ definitions */ /** the first seven of the following are fixed, the rest you change if you need to **/ -#define IRQ_EMU 0 /* Emulation */ -#define IRQ_RST 1 /* reset */ -#define IRQ_NMI 2 /* Non Maskable */ -#define IRQ_EVX 3 /* Exception */ -#define IRQ_UNUSED 4 /* - unused interrupt*/ -#define IRQ_HWERR 5 /* Hardware Error */ -#define IRQ_CORETMR 6 /* Core timer */ - -#define BFIN_IRQ(x) ((x) + 7) - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ -#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ -#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ -#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ -#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ -#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ -#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ -#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ -#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ -#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ -#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ -#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ -#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ -#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ -#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ -#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ -#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ -#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ -#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ -#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ -#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ -#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ -#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ -#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ -#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ -#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ -#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ -#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ -#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ -#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ -#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ -#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ -#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ -#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ -#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ -#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ -#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ -#define IRQ_TWI IRQ_TWI0 /* TWI Interrupt */ -#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ -#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ -#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ -#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ -#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ -#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ -#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ -#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ -#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ -#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ -#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ -#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ -#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ -#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ -#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ -#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ -#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ -#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ -#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ -#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ -#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ -#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ -#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ -#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ -#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ -#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ -#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ -#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ -#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ -#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ -#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ -#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ -#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ -#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ -#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ -#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ -#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ -#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ -#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ -#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ -#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ - -#define SYS_IRQS IRQ_PINT3 - -#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) -#define IRQ_PA0 BFIN_PA_IRQ(0) -#define IRQ_PA1 BFIN_PA_IRQ(1) -#define IRQ_PA2 BFIN_PA_IRQ(2) -#define IRQ_PA3 BFIN_PA_IRQ(3) -#define IRQ_PA4 BFIN_PA_IRQ(4) -#define IRQ_PA5 BFIN_PA_IRQ(5) -#define IRQ_PA6 BFIN_PA_IRQ(6) -#define IRQ_PA7 BFIN_PA_IRQ(7) -#define IRQ_PA8 BFIN_PA_IRQ(8) -#define IRQ_PA9 BFIN_PA_IRQ(9) -#define IRQ_PA10 BFIN_PA_IRQ(10) -#define IRQ_PA11 BFIN_PA_IRQ(11) -#define IRQ_PA12 BFIN_PA_IRQ(12) -#define IRQ_PA13 BFIN_PA_IRQ(13) -#define IRQ_PA14 BFIN_PA_IRQ(14) -#define IRQ_PA15 BFIN_PA_IRQ(15) - -#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) -#define IRQ_PB0 BFIN_PB_IRQ(0) -#define IRQ_PB1 BFIN_PB_IRQ(1) -#define IRQ_PB2 BFIN_PB_IRQ(2) -#define IRQ_PB3 BFIN_PB_IRQ(3) -#define IRQ_PB4 BFIN_PB_IRQ(4) -#define IRQ_PB5 BFIN_PB_IRQ(5) -#define IRQ_PB6 BFIN_PB_IRQ(6) -#define IRQ_PB7 BFIN_PB_IRQ(7) -#define IRQ_PB8 BFIN_PB_IRQ(8) -#define IRQ_PB9 BFIN_PB_IRQ(9) -#define IRQ_PB10 BFIN_PB_IRQ(10) -#define IRQ_PB11 BFIN_PB_IRQ(11) -#define IRQ_PB12 BFIN_PB_IRQ(12) -#define IRQ_PB13 BFIN_PB_IRQ(13) -#define IRQ_PB14 BFIN_PB_IRQ(14) -#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ - -#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) -#define IRQ_PC0 BFIN_PC_IRQ(0) -#define IRQ_PC1 BFIN_PC_IRQ(1) -#define IRQ_PC2 BFIN_PC_IRQ(2) -#define IRQ_PC3 BFIN_PC_IRQ(3) -#define IRQ_PC4 BFIN_PC_IRQ(4) -#define IRQ_PC5 BFIN_PC_IRQ(5) -#define IRQ_PC6 BFIN_PC_IRQ(6) -#define IRQ_PC7 BFIN_PC_IRQ(7) -#define IRQ_PC8 BFIN_PC_IRQ(8) -#define IRQ_PC9 BFIN_PC_IRQ(9) -#define IRQ_PC10 BFIN_PC_IRQ(10) -#define IRQ_PC11 BFIN_PC_IRQ(11) -#define IRQ_PC12 BFIN_PC_IRQ(12) -#define IRQ_PC13 BFIN_PC_IRQ(13) -#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ -#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ - -#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) -#define IRQ_PD0 BFIN_PD_IRQ(0) -#define IRQ_PD1 BFIN_PD_IRQ(1) -#define IRQ_PD2 BFIN_PD_IRQ(2) -#define IRQ_PD3 BFIN_PD_IRQ(3) -#define IRQ_PD4 BFIN_PD_IRQ(4) -#define IRQ_PD5 BFIN_PD_IRQ(5) -#define IRQ_PD6 BFIN_PD_IRQ(6) -#define IRQ_PD7 BFIN_PD_IRQ(7) -#define IRQ_PD8 BFIN_PD_IRQ(8) -#define IRQ_PD9 BFIN_PD_IRQ(9) -#define IRQ_PD10 BFIN_PD_IRQ(10) -#define IRQ_PD11 BFIN_PD_IRQ(11) -#define IRQ_PD12 BFIN_PD_IRQ(12) -#define IRQ_PD13 BFIN_PD_IRQ(13) -#define IRQ_PD14 BFIN_PD_IRQ(14) -#define IRQ_PD15 BFIN_PD_IRQ(15) - -#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) -#define IRQ_PE0 BFIN_PE_IRQ(0) -#define IRQ_PE1 BFIN_PE_IRQ(1) -#define IRQ_PE2 BFIN_PE_IRQ(2) -#define IRQ_PE3 BFIN_PE_IRQ(3) -#define IRQ_PE4 BFIN_PE_IRQ(4) -#define IRQ_PE5 BFIN_PE_IRQ(5) -#define IRQ_PE6 BFIN_PE_IRQ(6) -#define IRQ_PE7 BFIN_PE_IRQ(7) -#define IRQ_PE8 BFIN_PE_IRQ(8) -#define IRQ_PE9 BFIN_PE_IRQ(9) -#define IRQ_PE10 BFIN_PE_IRQ(10) -#define IRQ_PE11 BFIN_PE_IRQ(11) -#define IRQ_PE12 BFIN_PE_IRQ(12) -#define IRQ_PE13 BFIN_PE_IRQ(13) -#define IRQ_PE14 BFIN_PE_IRQ(14) -#define IRQ_PE15 BFIN_PE_IRQ(15) - -#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) -#define IRQ_PF0 BFIN_PF_IRQ(0) -#define IRQ_PF1 BFIN_PF_IRQ(1) -#define IRQ_PF2 BFIN_PF_IRQ(2) -#define IRQ_PF3 BFIN_PF_IRQ(3) -#define IRQ_PF4 BFIN_PF_IRQ(4) -#define IRQ_PF5 BFIN_PF_IRQ(5) -#define IRQ_PF6 BFIN_PF_IRQ(6) -#define IRQ_PF7 BFIN_PF_IRQ(7) -#define IRQ_PF8 BFIN_PF_IRQ(8) -#define IRQ_PF9 BFIN_PF_IRQ(9) -#define IRQ_PF10 BFIN_PF_IRQ(10) -#define IRQ_PF11 BFIN_PF_IRQ(11) -#define IRQ_PF12 BFIN_PF_IRQ(12) -#define IRQ_PF13 BFIN_PF_IRQ(13) -#define IRQ_PF14 BFIN_PF_IRQ(14) -#define IRQ_PF15 BFIN_PF_IRQ(15) - -#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) -#define IRQ_PG0 BFIN_PG_IRQ(0) -#define IRQ_PG1 BFIN_PG_IRQ(1) -#define IRQ_PG2 BFIN_PG_IRQ(2) -#define IRQ_PG3 BFIN_PG_IRQ(3) -#define IRQ_PG4 BFIN_PG_IRQ(4) -#define IRQ_PG5 BFIN_PG_IRQ(5) -#define IRQ_PG6 BFIN_PG_IRQ(6) -#define IRQ_PG7 BFIN_PG_IRQ(7) -#define IRQ_PG8 BFIN_PG_IRQ(8) -#define IRQ_PG9 BFIN_PG_IRQ(9) -#define IRQ_PG10 BFIN_PG_IRQ(10) -#define IRQ_PG11 BFIN_PG_IRQ(11) -#define IRQ_PG12 BFIN_PG_IRQ(12) -#define IRQ_PG13 BFIN_PG_IRQ(13) -#define IRQ_PG14 BFIN_PG_IRQ(14) -#define IRQ_PG15 BFIN_PG_IRQ(15) - -#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) -#define IRQ_PH0 BFIN_PH_IRQ(0) -#define IRQ_PH1 BFIN_PH_IRQ(1) -#define IRQ_PH2 BFIN_PH_IRQ(2) -#define IRQ_PH3 BFIN_PH_IRQ(3) -#define IRQ_PH4 BFIN_PH_IRQ(4) -#define IRQ_PH5 BFIN_PH_IRQ(5) -#define IRQ_PH6 BFIN_PH_IRQ(6) -#define IRQ_PH7 BFIN_PH_IRQ(7) -#define IRQ_PH8 BFIN_PH_IRQ(8) -#define IRQ_PH9 BFIN_PH_IRQ(9) -#define IRQ_PH10 BFIN_PH_IRQ(10) -#define IRQ_PH11 BFIN_PH_IRQ(11) -#define IRQ_PH12 BFIN_PH_IRQ(12) -#define IRQ_PH13 BFIN_PH_IRQ(13) -#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ -#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ - -#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) -#define IRQ_PI0 BFIN_PI_IRQ(0) -#define IRQ_PI1 BFIN_PI_IRQ(1) -#define IRQ_PI2 BFIN_PI_IRQ(2) -#define IRQ_PI3 BFIN_PI_IRQ(3) -#define IRQ_PI4 BFIN_PI_IRQ(4) -#define IRQ_PI5 BFIN_PI_IRQ(5) -#define IRQ_PI6 BFIN_PI_IRQ(6) -#define IRQ_PI7 BFIN_PI_IRQ(7) -#define IRQ_PI8 BFIN_PI_IRQ(8) -#define IRQ_PI9 BFIN_PI_IRQ(9) -#define IRQ_PI10 BFIN_PI_IRQ(10) -#define IRQ_PI11 BFIN_PI_IRQ(11) -#define IRQ_PI12 BFIN_PI_IRQ(12) -#define IRQ_PI13 BFIN_PI_IRQ(13) -#define IRQ_PI14 BFIN_PI_IRQ(14) -#define IRQ_PI15 BFIN_PI_IRQ(15) - -#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) -#define IRQ_PJ0 BFIN_PJ_IRQ(0) -#define IRQ_PJ1 BFIN_PJ_IRQ(1) -#define IRQ_PJ2 BFIN_PJ_IRQ(2) -#define IRQ_PJ3 BFIN_PJ_IRQ(3) -#define IRQ_PJ4 BFIN_PJ_IRQ(4) -#define IRQ_PJ5 BFIN_PJ_IRQ(5) -#define IRQ_PJ6 BFIN_PJ_IRQ(6) -#define IRQ_PJ7 BFIN_PJ_IRQ(7) -#define IRQ_PJ8 BFIN_PJ_IRQ(8) -#define IRQ_PJ9 BFIN_PJ_IRQ(9) -#define IRQ_PJ10 BFIN_PJ_IRQ(10) -#define IRQ_PJ11 BFIN_PJ_IRQ(11) -#define IRQ_PJ12 BFIN_PJ_IRQ(12) -#define IRQ_PJ13 BFIN_PJ_IRQ(13) -#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ -#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ +#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ #define GPIO_IRQ_BASE IRQ_PA0 @@ -345,6 +344,34 @@ Events (highest priority) EMU 0 #define NR_IRQS (SYS_IRQS+1) #endif +/* For compatibility reasons with existing code */ + +#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR +#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR +#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR +#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR +#define IRQ_SPI0_ERR IRQ_SPI0_ERROR +#define IRQ_UART0_ERR IRQ_UART0_ERROR +#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR +#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR +#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR +#define IRQ_SPI1_ERR IRQ_SPI1_ERROR +#define IRQ_SPI2_ERR IRQ_SPI2_ERROR +#define IRQ_UART1_ERR IRQ_UART1_ERROR +#define IRQ_UART2_ERR IRQ_UART2_ERROR +#define IRQ_CAN0_ERR IRQ_CAN0_ERROR +#define IRQ_MXVR_ERR IRQ_MXVR_ERROR +#define IRQ_EPP1_ERR IRQ_EPP1_ERROR +#define IRQ_EPP2_ERR IRQ_EPP2_ERROR +#define IRQ_UART3_ERR IRQ_UART3_ERROR +#define IRQ_HOST_ERR IRQ_HOST_ERROR +#define IRQ_PIXC_ERR IRQ_PIXC_ERROR +#define IRQ_NFC_ERR IRQ_NFC_ERROR +#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR +#define IRQ_CAN1_ERR IRQ_CAN1_ERROR +#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR + + #define IVG7 7 #define IVG8 8 #define IVG9 9 -- cgit v1.2.3 From 1d487f468de75b8a5c664db60e106935f9dc753b Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Thu, 11 Oct 2007 00:30:56 +0800 Subject: Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/defBF544.h | 1 + include/asm-blackfin/mach-bf548/defBF548.h | 2 ++ include/asm-blackfin/mach-bf548/defBF549.h | 2 ++ include/asm-blackfin/mach-bf548/defBF54x_base.h | 3 +++ 4 files changed, 8 insertions(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index dd955dcd39b..760307e34b9 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -81,6 +81,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index 8d4214e0807..70af33c963b 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -120,6 +120,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ @@ -139,6 +140,7 @@ /* SPI2 Registers */ +#define SPI2_REGBASE 0xffc02400 #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index c2f4734da48..50b3fe55ef0 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -121,6 +121,7 @@ /* Two Wire Interface Registers (TWI1) */ +#define TWI1_REGBASE 0xffc02200 #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ @@ -140,6 +141,7 @@ /* SPI2 Registers */ +#define SPI2_REGBASE 0xffc02400 #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 895ddd40a83..e2632db74ba 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -109,6 +109,7 @@ /* SPI0 Registers */ +#define SPI0_REGBASE 0xffc00500 #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ @@ -121,6 +122,7 @@ /* Two Wire Interface Registers (TWI0) */ +#define TWI0_REGBASE 0xffc00700 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ @@ -978,6 +980,7 @@ /* SPI1 Registers */ +#define SPI1_REGBASE 0xffc02300 #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ -- cgit v1.2.3 From 2b39331a282c3a03415653d4e188910a11c9db8a Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 10 Oct 2007 16:58:49 +0800 Subject: Blackfin arch: Comply with revised Anomaly Workarounds for BF533 05000311 and BF561 05000323 Comply with revised Anomaly Workarounds for BF533 05000311 and BF561 05000323 accoring to BF533 anomaly sheet Rev. A 09/04/07 Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf548/anomaly.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-blackfin/mach-bf548') diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 0d12dbe5232..c5b63759cde 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -80,5 +80,6 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) #endif -- cgit v1.2.3